diff mbox series

[02/33] common/cnxk: accommodate change in aura field width

Message ID	20240910085909.1514457-3-ndabilpuram@marvell.com (mailing list archive)
State	Changes Requested
Delegated to:	Jerin Jacob
Headers	From: Nithin Dabilpuram <ndabilpuram@marvell.com> To: <jerinj@marvell.com>, Nithin Dabilpuram <ndabilpuram@marvell.com>, "Kiran Kumar K" <kirankumark@marvell.com>, Sunil Kumar Kori <skori@marvell.com>, Satha Rao <skoteshwar@marvell.com>, Harman Kalra <hkalra@marvell.com> CC: <dev@dpdk.org>, Ashwin Sekhar T K <asekhar@marvell.com> Subject: [PATCH 02/33] common/cnxk: accommodate change in aura field width Date: Tue, 10 Sep 2024 14:28:38 +0530 Message-ID: <20240910085909.1514457-3-ndabilpuram@marvell.com> In-Reply-To: <20240910085909.1514457-1-ndabilpuram@marvell.com> References: <20240910085909.1514457-1-ndabilpuram@marvell.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain Precedence: list Errors-To: dev-bounces@dpdk.org
Series	add Marvell cn20k SOC support for mempool and net \| [00/33] add Marvell cn20k SOC support for mempool and net [01/33] mempool/cnxk: add cn20k PCI device ids [02/33] common/cnxk: accommodate change in aura field width [03/33] common/cnxk: use new NPA aq enq mbox for cn20k [04/33] mempool/cnxk: initialize mempool ops for cn20k [05/33] net/cnxk: added telemetry support do dump SA information [06/33] net/cnxk: handle timestamp correctly for VF [07/33] net/cnxk: update Rx offloads to handle timestamp [08/33] event/cnxk: handle timestamp for event mode [09/33] net/cnxk: update mbuf and rearm data for Rx inject packets [10/33] common/cnxk: remove restriction to clear RPM stats [11/33] common/cnxk: allow MAC address set/add with active VFs [12/33] net/cnxk: move PMD function defines to common code [13/33] common/cnxk: add cn20k NIX register definitions [14/33] common/cnxk: support NIX queue config for cn20k [15/33] common/cnxk: support bandwidth profile for cn20k [16/33] common/cnxk: support NIX debug for cn20k [17/33] common/cnxk: add RSS support for cn20k [18/33] net/cnxk: add cn20k base control path support [19/33] net/cnxk: support Rx function select for cn20k [20/33] net/cnxk: support Tx function select for cn20k [21/33] net/cnxk: support Rx burst scalar for cn20k [22/33] net/cnxk: support Rx burst vector for cn20k [23/33] net/cnxk: support Tx burst scalar for cn20k [24/33] net/cnxk: support Tx multi-seg in cn20k [25/33] net/cnxk: support Tx burst vector for cn20k [26/33] net/cnxk: support Tx multi-seg in vector for cn20k [27/33] common/cnxk: add flush wait after write of inline ctx [28/33] common/cnxk: fix CPT HW word size for outbound SA [29/33] net/cnxk: add PMD APIs for IPsec SA base and flush [30/33] net/cnxk: add PMD APIs to submit CPT instruction [31/33] net/cnxk: add PMD API to retrieve CPT queue statistics [32/33] net/cnxk: add option to enable custom inbound sa usage [33/33] net/cnxk: add PMD API to retrieve the model string

Checks

Context	Check	Description
ci/checkpatch	success	coding style OK

Commit Message

Nithin Dabilpuram Sept. 10, 2024, 8:58 a.m. UTC

From: Ashwin Sekhar T K <asekhar@marvell.com>

Aura field width has changed from 20 bits to 17 bits in
cn20k. Adjust the bit fields accordingly for register
reads/writes.

Signed-off-by: Ashwin Sekhar T K <asekhar@marvell.com>
---
 drivers/common/cnxk/roc_npa.h | 24 ++++++++++++++++--------
 1 file changed, 16 insertions(+), 8 deletions(-)

diff mbox series

Patch

diff --git a/drivers/common/cnxk/roc_npa.h b/drivers/common/cnxk/roc_npa.h
index 4ad5f044b5..fbf75b2fca 100644
--- a/drivers/common/cnxk/roc_npa.h
+++ b/drivers/common/cnxk/roc_npa.h
@@ -16,6 +16,7 @@ 
 #else
 #include "roc_io_generic.h"
 #endif
+#include "roc_model.h"
 #include "roc_npa_dp.h"
 
 #define ROC_AURA_OP_LIMIT_MASK (BIT_ULL(36) - 1)
@@ -68,11 +69,12 @@  roc_npa_aura_op_alloc(uint64_t aura_handle, const int drop)
 static inline uint64_t
 roc_npa_aura_op_cnt_get(uint64_t aura_handle)
 {
-	uint64_t wdata;
+	uint64_t wdata, shift;
 	int64_t *addr;
 	uint64_t reg;
 
-	wdata = roc_npa_aura_handle_to_aura(aura_handle) << 44;
+	shift = roc_model_is_cn20k() ? 47 : 44;
+	wdata = roc_npa_aura_handle_to_aura(aura_handle) << shift;
 	addr = (int64_t *)(roc_npa_aura_handle_to_base(aura_handle) +
 			   NPA_LF_AURA_OP_CNT);
 	reg = roc_atomic64_add_nosync(wdata, addr);
@@ -87,11 +89,13 @@  static inline void
 roc_npa_aura_op_cnt_set(uint64_t aura_handle, const int sign, uint64_t count)
 {
 	uint64_t reg = count & (BIT_ULL(36) - 1);
+	uint64_t shift;
 
 	if (sign)
 		reg |= BIT_ULL(43); /* CNT_ADD */
 
-	reg |= (roc_npa_aura_handle_to_aura(aura_handle) << 44);
+	shift = roc_model_is_cn20k() ? 47 : 44;
+	reg |= (roc_npa_aura_handle_to_aura(aura_handle) << shift);
 
 	plt_write64(reg, roc_npa_aura_handle_to_base(aura_handle) +
 				 NPA_LF_AURA_OP_CNT);
@@ -100,11 +104,12 @@  roc_npa_aura_op_cnt_set(uint64_t aura_handle, const int sign, uint64_t count)
 static inline uint64_t
 roc_npa_aura_op_limit_get(uint64_t aura_handle)
 {
-	uint64_t wdata;
+	uint64_t wdata, shift;
 	int64_t *addr;
 	uint64_t reg;
 
-	wdata = roc_npa_aura_handle_to_aura(aura_handle) << 44;
+	shift = roc_model_is_cn20k() ? 47 : 44;
+	wdata = roc_npa_aura_handle_to_aura(aura_handle) << shift;
 	addr = (int64_t *)(roc_npa_aura_handle_to_base(aura_handle) +
 			   NPA_LF_AURA_OP_LIMIT);
 	reg = roc_atomic64_add_nosync(wdata, addr);
@@ -119,8 +124,10 @@  static inline void
 roc_npa_aura_op_limit_set(uint64_t aura_handle, uint64_t limit)
 {
 	uint64_t reg = limit & ROC_AURA_OP_LIMIT_MASK;
+	uint64_t shift;
 
-	reg |= (roc_npa_aura_handle_to_aura(aura_handle) << 44);
+	shift = roc_model_is_cn20k() ? 47 : 44;
+	reg |= (roc_npa_aura_handle_to_aura(aura_handle) << shift);
 
 	plt_write64(reg, roc_npa_aura_handle_to_base(aura_handle) +
 				 NPA_LF_AURA_OP_LIMIT);
@@ -129,11 +136,12 @@  roc_npa_aura_op_limit_set(uint64_t aura_handle, uint64_t limit)
 static inline uint64_t
 roc_npa_aura_op_available(uint64_t aura_handle)
 {
-	uint64_t wdata;
+	uint64_t wdata, shift;
 	uint64_t reg;
 	int64_t *addr;
 
-	wdata = roc_npa_aura_handle_to_aura(aura_handle) << 44;
+	shift = roc_model_is_cn20k() ? 47 : 44;
+	wdata = roc_npa_aura_handle_to_aura(aura_handle) << shift;
 	addr = (int64_t *)(roc_npa_aura_handle_to_base(aura_handle) +
 			   NPA_LF_POOL_OP_AVAILABLE);
 	reg = roc_atomic64_add_nosync(wdata, addr);