[v3,5/9] examples/l3fwd: use accelerated CRC on riscv
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Commit Message
When the RISC-V Zbc (carryless multiplication) extension is present, an
implementation of CRC hashing using hardware instructions is available.
Use it rather than jhash.
Signed-off-by: Daniel Gregory <daniel.gregory@bytedance.com>
---
examples/l3fwd/l3fwd_em.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
@@ -29,7 +29,7 @@
#include "l3fwd_event.h"
#include "em_route_parse.c"
-#if defined(RTE_ARCH_X86) || defined(__ARM_FEATURE_CRC32)
+#if defined(RTE_ARCH_X86) || defined(__ARM_FEATURE_CRC32) || defined(RTE_RISCV_FEATURE_ZBC)
#define EM_HASH_CRC 1
#endif