From patchwork Tue Aug 27 15:32:24 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Gregory X-Patchwork-Id: 143408 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 2E17345879; Tue, 27 Aug 2024 17:33:16 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 4AA8A40E64; Tue, 27 Aug 2024 17:32:51 +0200 (CEST) Received: from mail-lf1-f41.google.com (mail-lf1-f41.google.com [209.85.167.41]) by mails.dpdk.org (Postfix) with ESMTP id A37A140E3F for ; Tue, 27 Aug 2024 17:32:47 +0200 (CEST) Received: by mail-lf1-f41.google.com with SMTP id 2adb3069b0e04-533488ffaf7so7651534e87.0 for ; Tue, 27 Aug 2024 08:32:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bytedance.com; s=google; t=1724772767; x=1725377567; darn=dpdk.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ejIhUJroe4N2Yb/FgUtopm3XfRUag0wCssM0dj8Hhp4=; b=AX2NSpBT647MX4evy2S5dM39NcNaBwCYSglCgSy1FQg3V/quD0XtQQ/Yxm05K1StJk Q0IsOrCODaF4NzKQM7TSYqYja0bum0oTHFllFXmLkf2/wGAKSfx1tMI+4JGsfuXWowu6 3ZPgnci+V9k7wG0a9T1bm/xdstcXj+fpyihRFKybhN+99pKpSaGkIfnjSWKKd5FPXhS1 J/GsYLr/bQoLTzT6o6AhvBemQvSM52Ynoh8nDyJ/npPDjU9KHalOk4Qf4RljCUaUvkC1 bCF7E8bUIqxWV7rCzdQBSEDaTMq70aBxkzqKg54qv5IFol0RMQMQVpr0z0h0P8Eo8Yfg RdYQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1724772767; x=1725377567; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ejIhUJroe4N2Yb/FgUtopm3XfRUag0wCssM0dj8Hhp4=; b=db+tnxLKyPzKIXp8E0f/k4Uj1lA2FPcyCcy6xr1cdwwviQJsi8iL9Cz4+J3MAV/31v pz0v7/Zezp1z783Zyv7i1svVHj5w0saRHaSczmhzfUtUEsDfkm5wX+v3NKCAJm3+8lrS QlZbpSQDP7Kg9Y9oYKwUYKs780SxbWcydjrr+3RRCl84jxgxHn/tPQe+8x5+BVgFw74F sC+CWbF7hO9y89aNkx4FdNpCtt/j+Yux0n748zzyu5Ry7E33xHkhfpI8iudHcwpgv3yn bAOXiOeuLJMGKIrLdmkWd0znNZDKB5DQBgZtYONWr9IEBG6MUHpOv6VnnO7KHZONOit4 l2rg== X-Gm-Message-State: AOJu0Yx4RQ7gaOSBU35NGz1mRZ2fK5zQTRDVDUq1eyUNfOHjjiKqQXKs 6WIIxPhq4cAyukJIEBsfbMEHAPqW+Obps5FdZjPU9/tqL8JnMk6R+7/uhBxLcTE= X-Google-Smtp-Source: AGHT+IFUWWUTM/tLSSDE7rSPx/FXRcJqi+psUrnWSd3YrzzXgPev0iMvygInMDL8psnj0lSk2UiSsg== X-Received: by 2002:a05:6512:3f19:b0:52c:e170:9d38 with SMTP id 2adb3069b0e04-5344e3dab0bmr2267227e87.31.1724772766959; Tue, 27 Aug 2024 08:32:46 -0700 (PDT) Received: from C02FF2N1MD6T.bytedance.net ([93.115.195.2]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a86e582da41sm122323066b.109.2024.08.27.08.32.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 27 Aug 2024 08:32:46 -0700 (PDT) From: Daniel Gregory To: Stanislaw Kardach , Bruce Richardson Cc: dev@dpdk.org, Punit Agrawal , Liang Ma , Pengcheng Wang , Chunsong Feng , Daniel Gregory Subject: [PATCH v3 4/9] config/riscv: add qemu crossbuild target Date: Tue, 27 Aug 2024 16:32:24 +0100 Message-Id: <20240827153230.52880-5-daniel.gregory@bytedance.com> X-Mailer: git-send-email 2.39.3 (Apple Git-146) In-Reply-To: <20240827153230.52880-1-daniel.gregory@bytedance.com> References: <20240712154645.80622-1-daniel.gregory@bytedance.com> <20240827153230.52880-1-daniel.gregory@bytedance.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org A new cross-compilation target that has extensions that DPDK uses and QEMU supports. Initially, this is just the Zbc extension for hardware CRC support. Signed-off-by: Daniel Gregory --- config/riscv/meson.build | 3 ++- config/riscv/riscv64_qemu_linux_gcc | 17 +++++++++++++++++ .../linux_gsg/cross_build_dpdk_for_riscv.rst | 5 +++++ 3 files changed, 24 insertions(+), 1 deletion(-) create mode 100644 config/riscv/riscv64_qemu_linux_gcc diff --git a/config/riscv/meson.build b/config/riscv/meson.build index 5d8411b254..337b26bbac 100644 --- a/config/riscv/meson.build +++ b/config/riscv/meson.build @@ -43,7 +43,8 @@ vendor_generic = { ['RTE_MAX_NUMA_NODES', 2] ], 'arch_config': { - 'generic': {'machine_args': ['-march=rv64gc']} + 'generic': {'machine_args': ['-march=rv64gc']}, + 'qemu': {'machine_args': ['-march=rv64gc_zbc']}, } } diff --git a/config/riscv/riscv64_qemu_linux_gcc b/config/riscv/riscv64_qemu_linux_gcc new file mode 100644 index 0000000000..007cc98885 --- /dev/null +++ b/config/riscv/riscv64_qemu_linux_gcc @@ -0,0 +1,17 @@ +[binaries] +c = ['ccache', 'riscv64-linux-gnu-gcc'] +cpp = ['ccache', 'riscv64-linux-gnu-g++'] +ar = 'riscv64-linux-gnu-ar' +strip = 'riscv64-linux-gnu-strip' +pcap-config = '' + +[host_machine] +system = 'linux' +cpu_family = 'riscv64' +cpu = 'rv64gc_zbc' +endian = 'little' + +[properties] +vendor_id = 'generic' +arch_id = 'qemu' +pkg_config_libdir = '/usr/lib/riscv64-linux-gnu/pkgconfig' diff --git a/doc/guides/linux_gsg/cross_build_dpdk_for_riscv.rst b/doc/guides/linux_gsg/cross_build_dpdk_for_riscv.rst index 7d7f7ac72b..c3b67671a0 100644 --- a/doc/guides/linux_gsg/cross_build_dpdk_for_riscv.rst +++ b/doc/guides/linux_gsg/cross_build_dpdk_for_riscv.rst @@ -110,6 +110,11 @@ Currently the following targets are supported: * SiFive U740 SoC: ``config/riscv/riscv64_sifive_u740_linux_gcc`` +* QEMU: ``config/riscv/riscv64_qemu_linux_gcc`` + + * A target with all the extensions that QEMU supports that DPDK has a use for + (currently ``rv64gc_zbc``). Requires QEMU version 7.0.0 or newer. + To add a new target support, ``config/riscv/meson.build`` has to be modified by adding a new vendor/architecture id and a corresponding cross-file has to be added to ``config/riscv`` directory.