diff mbox series

[v2,07/25] net/axgbe: enable PLL control for fixed PHY modes only

Message ID 20240507124305.2318-7-venkatkumar.ande@amd.com (mailing list archive)
State Changes Requested, archived
Delegated to: Ferruh Yigit
Headers
Series [v2,01/25] net/axgbe: fix mdio access for non-zero ports and CL45 PHYs |

Checks

Context Check Description
ci/checkpatch success coding style OK

Commit Message

Venkat Kumar Ande May 7, 2024, 12:42 p.m. UTC 
PLL control setting(RRC) is needed only in fixed PHY configuration to
fix the peer-peer issues. Without the PLL control setting, the link up
takes longer time in a fixed phy configuration.

Without the fix the user will not get the link come UP.

Driver implements SW RRC for Autoneg On configuration, hence PLL control
setting (RRC) is not needed for AN On configuration, and can be skipped.

Also, PLL re-initialization is not needed for PHY Power Off and RRC
commands. Otherwise, they lead to mailbox errors. Added the changes
accordingly.

Fixes: 09b0a36cc7ae ("net/axgbe: toggle PLL settings during rate change")
Cc: stable@dpdk.org

Signed-off-by: Venkat Kumar Ande <venkatkumar.ande@amd.com>
---
 drivers/net/axgbe/axgbe_phy_impl.c | 10 ++++++++--
 1 file changed, 8 insertions(+), 2 deletions(-)

Comments

Sebastian, Selwin May 20, 2024, 10:41 a.m. UTC | #1 
[AMD Official Use Only - AMD Internal Distribution Only]

Acked-by: Selwin Sebastian<selwin.sebastian@amd.com>

-----Original Message-----
From: Ande, Venkat Kumar <VenkatKumar.Ande@amd.com>
Sent: Tuesday, May 7, 2024 6:13 PM
To: dev@dpdk.org
Cc: Sebastian, Selwin <Selwin.Sebastian@amd.com>; Ande, Venkat Kumar <VenkatKumar.Ande@amd.com>; stable@dpdk.org
Subject: [PATCH v2 07/25] net/axgbe: enable PLL control for fixed PHY modes only

PLL control setting(RRC) is needed only in fixed PHY configuration to fix the peer-peer issues. Without the PLL control setting, the link up takes longer time in a fixed phy configuration.

Without the fix the user will not get the link come UP.

Driver implements SW RRC for Autoneg On configuration, hence PLL control setting (RRC) is not needed for AN On configuration, and can be skipped.

Also, PLL re-initialization is not needed for PHY Power Off and RRC commands. Otherwise, they lead to mailbox errors. Added the changes accordingly.

Fixes: 09b0a36cc7ae ("net/axgbe: toggle PLL settings during rate change")
Cc: stable@dpdk.org

Signed-off-by: Venkat Kumar Ande <venkatkumar.ande@amd.com>
---
 drivers/net/axgbe/axgbe_phy_impl.c | 10 ++++++++--
 1 file changed, 8 insertions(+), 2 deletions(-)

diff --git a/drivers/net/axgbe/axgbe_phy_impl.c b/drivers/net/axgbe/axgbe_phy_impl.c
index f51830f800..9c2ae7bba0 100644
--- a/drivers/net/axgbe/axgbe_phy_impl.c
+++ b/drivers/net/axgbe/axgbe_phy_impl.c
@@ -1228,6 +1228,10 @@ static void axgbe_phy_rx_reset(struct axgbe_port *pdata)

 static void axgbe_phy_pll_ctrl(struct axgbe_port *pdata, bool enable)  {
+       /* PLL_CTRL feature needs to be enabled for fixed PHY modes (Non-Autoneg) only */
+       if (pdata->phy.autoneg != AUTONEG_DISABLE)
+               return;
+
        XMDIO_WRITE_BITS(pdata, MDIO_MMD_PMAPMD, MDIO_VEND2_PMA_MISC_CTRL0,
                        XGBE_PMA_PLL_CTRL_MASK,
                        enable ? XGBE_PMA_PLL_CTRL_SET
@@ -1272,8 +1276,10 @@ static void axgbe_phy_perform_ratechange(struct axgbe_port *pdata,
        axgbe_phy_rx_reset(pdata);

 reenable_pll:
-        /* Re-enable the PLL control */
-       axgbe_phy_pll_ctrl(pdata, true);
+       /* Enable PLL re-initialization, not needed for PHY Power Off and RRC cmds */
+       if (cmd != AXGBE_MB_CMD_POWER_OFF &&
+           cmd != AXGBE_MB_CMD_RRC)
+               axgbe_phy_pll_ctrl(pdata, true);

        PMD_DRV_LOG(NOTICE, "firmware mailbox command did not complete\n");  }
--
2.34.1
Ferruh Yigit May 20, 2024, 11:25 a.m. UTC | #2 
On 5/7/2024 1:42 PM, Venkat Kumar Ande wrote:
> PLL control setting(RRC) is needed only in fixed PHY configuration to
> fix the peer-peer issues. Without the PLL control setting, the link up
> takes longer time in a fixed phy configuration.
> 
> Without the fix the user will not get the link come UP.
> 
> Driver implements SW RRC for Autoneg On configuration, hence PLL control
> setting (RRC) is not needed for AN On configuration, and can be skipped.
> 
> Also, PLL re-initialization is not needed for PHY Power Off and RRC
> commands. Otherwise, they lead to mailbox errors. Added the changes
> accordingly.
> 
> Fixes: 09b0a36cc7ae ("net/axgbe: toggle PLL settings during rate change")
> Cc: stable@dpdk.org
> 
> Signed-off-by: Venkat Kumar Ande <venkatkumar.ande@amd.com>
> 

Build fails with this patch.

'AXGBE_MB_CMD_POWER_OFF' & 'AXGBE_MB_CMD_RRC' are missing in the patch,
and they are added later in patch 17/25.


As this is only build fix related to the patch order, please keep Acks
from Selwin in next version (I mean keep ack tags embedded in next
version, so that no need to send new set of acks.)

Thanks,
ferruh
diff mbox series

Patch

diff --git a/drivers/net/axgbe/axgbe_phy_impl.c b/drivers/net/axgbe/axgbe_phy_impl.c
index f51830f800..9c2ae7bba0 100644
--- a/drivers/net/axgbe/axgbe_phy_impl.c
+++ b/drivers/net/axgbe/axgbe_phy_impl.c
@@ -1228,6 +1228,10 @@  static void axgbe_phy_rx_reset(struct axgbe_port *pdata)
 
 static void axgbe_phy_pll_ctrl(struct axgbe_port *pdata, bool enable)
 {
+	/* PLL_CTRL feature needs to be enabled for fixed PHY modes (Non-Autoneg) only */
+	if (pdata->phy.autoneg != AUTONEG_DISABLE)
+		return;
+
 	XMDIO_WRITE_BITS(pdata, MDIO_MMD_PMAPMD, MDIO_VEND2_PMA_MISC_CTRL0,
 			XGBE_PMA_PLL_CTRL_MASK,
 			enable ? XGBE_PMA_PLL_CTRL_SET
@@ -1272,8 +1276,10 @@  static void axgbe_phy_perform_ratechange(struct axgbe_port *pdata,
 	axgbe_phy_rx_reset(pdata);
 
 reenable_pll:
-	 /* Re-enable the PLL control */
-	axgbe_phy_pll_ctrl(pdata, true);
+	/* Enable PLL re-initialization, not needed for PHY Power Off and RRC cmds */
+	if (cmd != AXGBE_MB_CMD_POWER_OFF &&
+	    cmd != AXGBE_MB_CMD_RRC)
+		axgbe_phy_pll_ctrl(pdata, true);
 
 	PMD_DRV_LOG(NOTICE, "firmware mailbox command did not complete\n");
 }