diff mbox series

[v2,20/25] net/axgbe: replace mii generic macro for c45 with AXGBE

Message ID 20240507124305.2318-20-venkatkumar.ande@amd.com (mailing list archive)
State Changes Requested, archived
Delegated to: Ferruh Yigit
Headers
Series [v2,01/25] net/axgbe: fix mdio access for non-zero ports and CL45 PHYs |

Checks

Context Check Description
ci/checkpatch success coding style OK

Commit Message

Venkat Kumar Ande May 7, 2024, 12:43 p.m. UTC 
The axgbe driver reuses MII_ADDR_C45 for its own purpose. The values
derived with it are never passed to phylib or a linux MDIO bus driver.
In order that MII_ADDR_C45 can be removed, add an AXGBE specific

Signed-off-by: Venkat Kumar Ande <venkatkumar.ande@amd.com>
---
 drivers/net/axgbe/axgbe_common.h | 4 ++--
 drivers/net/axgbe/axgbe_dev.c    | 8 ++++----
 drivers/net/axgbe/axgbe_phy.h    | 2 +-
 3 files changed, 7 insertions(+), 7 deletions(-)

Comments

Sebastian, Selwin May 20, 2024, 10:43 a.m. UTC | #1 
[AMD Official Use Only - AMD Internal Distribution Only]

Acked-by: Selwin Sebastian<selwin.sebastian@amd.com>

-----Original Message-----
From: Ande, Venkat Kumar <VenkatKumar.Ande@amd.com>
Sent: Tuesday, May 7, 2024 6:13 PM
To: dev@dpdk.org
Cc: Sebastian, Selwin <Selwin.Sebastian@amd.com>; Ande, Venkat Kumar <VenkatKumar.Ande@amd.com>
Subject: [PATCH v2 20/25] net/axgbe: replace mii generic macro for c45 with AXGBE

The axgbe driver reuses MII_ADDR_C45 for its own purpose. The values derived with it are never passed to phylib or a linux MDIO bus driver.
In order that MII_ADDR_C45 can be removed, add an AXGBE specific

Signed-off-by: Venkat Kumar Ande <venkatkumar.ande@amd.com>
---
 drivers/net/axgbe/axgbe_common.h | 4 ++--
 drivers/net/axgbe/axgbe_dev.c    | 8 ++++----
 drivers/net/axgbe/axgbe_phy.h    | 2 +-
 3 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/drivers/net/axgbe/axgbe_common.h b/drivers/net/axgbe/axgbe_common.h
index 51532fb34a..1a43192630 100644
--- a/drivers/net/axgbe/axgbe_common.h
+++ b/drivers/net/axgbe/axgbe_common.h
@@ -1732,14 +1732,14 @@ do {                                                                    \
  */
 #define XMDIO_READ(_pdata, _mmd, _reg)                                 \
        ((_pdata)->hw_if.read_mmd_regs((_pdata), 0,                     \
-               MII_ADDR_C45 | ((_mmd) << 16) | ((_reg) & 0xffff)))
+               AXGBE_ADDR_C45 | ((_mmd) << 16) | ((_reg) & 0xffff)))

 #define XMDIO_READ_BITS(_pdata, _mmd, _reg, _mask)                     \
        (XMDIO_READ((_pdata), _mmd, _reg) & _mask)

 #define XMDIO_WRITE(_pdata, _mmd, _reg, _val)                          \
        ((_pdata)->hw_if.write_mmd_regs((_pdata), 0,                    \
-               MII_ADDR_C45 | ((_mmd) << 16) | ((_reg) & 0xffff), (_val)))
+               AXGBE_ADDR_C45 | ((_mmd) << 16) | ((_reg) & 0xffff), (_val)))

 #define XMDIO_WRITE_BITS(_pdata, _mmd, _reg, _mask, _val)              \
 do {                                                                   \
diff --git a/drivers/net/axgbe/axgbe_dev.c b/drivers/net/axgbe/axgbe_dev.c index fa7324efa7..ebe64295aa 100644
--- a/drivers/net/axgbe/axgbe_dev.c
+++ b/drivers/net/axgbe/axgbe_dev.c
@@ -207,8 +207,8 @@ static int axgbe_read_mmd_regs_v2(struct axgbe_port *pdata,
        unsigned int mmd_address, index, offset;
        int mmd_data;

-       if (mmd_reg & MII_ADDR_C45)
-               mmd_address = mmd_reg & ~MII_ADDR_C45;
+       if (mmd_reg & AXGBE_ADDR_C45)
+               mmd_address = mmd_reg & ~AXGBE_ADDR_C45;
        else
                mmd_address = (pdata->mdio_mmd << 16) | (mmd_reg & 0xffff);

@@ -241,8 +241,8 @@ static void axgbe_write_mmd_regs_v2(struct axgbe_port *pdata,  {
        unsigned int mmd_address, index, offset;

-       if (mmd_reg & MII_ADDR_C45)
-               mmd_address = mmd_reg & ~MII_ADDR_C45;
+       if (mmd_reg & AXGBE_ADDR_C45)
+               mmd_address = mmd_reg & ~AXGBE_ADDR_C45;
        else
                mmd_address = (pdata->mdio_mmd << 16) | (mmd_reg & 0xffff);

diff --git a/drivers/net/axgbe/axgbe_phy.h b/drivers/net/axgbe/axgbe_phy.h index 5b844e81cd..eee3afc370 100644
--- a/drivers/net/axgbe/axgbe_phy.h
+++ b/drivers/net/axgbe/axgbe_phy.h
@@ -16,7 +16,7 @@
 /* Or MII_ADDR_C45 into regnum for read/write on mii_bus to enable the 21 bit
  * IEEE 802.3ae clause 45 addressing mode used by 10GIGE phy chips.
  */
-#define MII_ADDR_C45 (1 << 30)
+#define AXGBE_ADDR_C45  (1 << 30)

 /* Basic mode status register. */
 #define BMSR_LSTATUS            0x0004  /* Link status */
--
2.34.1
Ferruh Yigit May 20, 2024, 11:25 a.m. UTC | #2 
On 5/7/2024 1:43 PM, Venkat Kumar Ande wrote:
> The axgbe driver reuses MII_ADDR_C45 for its own purpose. The values
> derived with it are never passed to phylib or a linux MDIO bus driver.
> In order that MII_ADDR_C45 can be removed, add an AXGBE specific
>

Last sentences feels like it is not finished, should it be something like:
"..., add an AXGBE specific macro."
diff mbox series

Patch

diff --git a/drivers/net/axgbe/axgbe_common.h b/drivers/net/axgbe/axgbe_common.h
index 51532fb34a..1a43192630 100644
--- a/drivers/net/axgbe/axgbe_common.h
+++ b/drivers/net/axgbe/axgbe_common.h
@@ -1732,14 +1732,14 @@  do {									\
  */
 #define XMDIO_READ(_pdata, _mmd, _reg)					\
 	((_pdata)->hw_if.read_mmd_regs((_pdata), 0,			\
-		MII_ADDR_C45 | ((_mmd) << 16) | ((_reg) & 0xffff)))
+		AXGBE_ADDR_C45 | ((_mmd) << 16) | ((_reg) & 0xffff)))
 
 #define XMDIO_READ_BITS(_pdata, _mmd, _reg, _mask)			\
 	(XMDIO_READ((_pdata), _mmd, _reg) & _mask)
 
 #define XMDIO_WRITE(_pdata, _mmd, _reg, _val)				\
 	((_pdata)->hw_if.write_mmd_regs((_pdata), 0,			\
-		MII_ADDR_C45 | ((_mmd) << 16) | ((_reg) & 0xffff), (_val)))
+		AXGBE_ADDR_C45 | ((_mmd) << 16) | ((_reg) & 0xffff), (_val)))
 
 #define XMDIO_WRITE_BITS(_pdata, _mmd, _reg, _mask, _val)		\
 do {									\
diff --git a/drivers/net/axgbe/axgbe_dev.c b/drivers/net/axgbe/axgbe_dev.c
index fa7324efa7..ebe64295aa 100644
--- a/drivers/net/axgbe/axgbe_dev.c
+++ b/drivers/net/axgbe/axgbe_dev.c
@@ -207,8 +207,8 @@  static int axgbe_read_mmd_regs_v2(struct axgbe_port *pdata,
 	unsigned int mmd_address, index, offset;
 	int mmd_data;
 
-	if (mmd_reg & MII_ADDR_C45)
-		mmd_address = mmd_reg & ~MII_ADDR_C45;
+	if (mmd_reg & AXGBE_ADDR_C45)
+		mmd_address = mmd_reg & ~AXGBE_ADDR_C45;
 	else
 		mmd_address = (pdata->mdio_mmd << 16) | (mmd_reg & 0xffff);
 
@@ -241,8 +241,8 @@  static void axgbe_write_mmd_regs_v2(struct axgbe_port *pdata,
 {
 	unsigned int mmd_address, index, offset;
 
-	if (mmd_reg & MII_ADDR_C45)
-		mmd_address = mmd_reg & ~MII_ADDR_C45;
+	if (mmd_reg & AXGBE_ADDR_C45)
+		mmd_address = mmd_reg & ~AXGBE_ADDR_C45;
 	else
 		mmd_address = (pdata->mdio_mmd << 16) | (mmd_reg & 0xffff);
 
diff --git a/drivers/net/axgbe/axgbe_phy.h b/drivers/net/axgbe/axgbe_phy.h
index 5b844e81cd..eee3afc370 100644
--- a/drivers/net/axgbe/axgbe_phy.h
+++ b/drivers/net/axgbe/axgbe_phy.h
@@ -16,7 +16,7 @@ 
 /* Or MII_ADDR_C45 into regnum for read/write on mii_bus to enable the 21 bit
  * IEEE 802.3ae clause 45 addressing mode used by 10GIGE phy chips.
  */
-#define MII_ADDR_C45 (1 << 30)
+#define AXGBE_ADDR_C45  (1 << 30)
 
 /* Basic mode status register. */
 #define BMSR_LSTATUS            0x0004  /* Link status */