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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by SN1PEPF00026369.mail.protection.outlook.com (10.167.241.134) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.7544.18 via Frontend Transport; Tue, 30 Apr 2024 20:22:14 +0000 Received: from driver-dev1.pensando.io (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Tue, 30 Apr 2024 15:22:13 -0500 From: Andrew Boyer To: CC: Andrew Boyer Subject: [PATCH v2 9/9] crypto/ionic: add stats support Date: Tue, 30 Apr 2024 13:21:44 -0700 Message-ID: <20240430202144.49899-10-andrew.boyer@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20240430202144.49899-1-andrew.boyer@amd.com> References: <20240419195310.21432-1-andrew.boyer@amd.com> <20240430202144.49899-1-andrew.boyer@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF00026369:EE_|DS0PR12MB9399:EE_ X-MS-Office365-Filtering-Correlation-Id: 5c2ea0d5-7483-42bc-30d6-08dc6953394b X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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Signed-off-by: Andrew Boyer --- drivers/crypto/ionic/ionic_crypto.h | 8 ++++ drivers/crypto/ionic/ionic_crypto_main.c | 48 ++++++++++++++++++++++++ drivers/crypto/ionic/ionic_crypto_ops.c | 33 +++++++++++++++- 3 files changed, 87 insertions(+), 2 deletions(-) diff --git a/drivers/crypto/ionic/ionic_crypto.h b/drivers/crypto/ionic/ionic_crypto.h index 69c17887fb..db87ea0490 100644 --- a/drivers/crypto/ionic/ionic_crypto.h +++ b/drivers/crypto/ionic/ionic_crypto.h @@ -174,6 +174,8 @@ struct iocpt_crypto_q { uint16_t flags; /* cacheline3 */ + struct rte_cryptodev_stats stats; + uint64_t enqueued_wdogs; uint64_t dequeued_wdogs; uint8_t wdog_iv[IOCPT_Q_WDOG_IV_LEN]; @@ -252,6 +254,8 @@ struct iocpt_dev { struct iocpt_qtype_info qtype_info[IOCPT_QTYPE_MAX]; uint8_t qtype_ver[IOCPT_QTYPE_MAX]; + + struct rte_cryptodev_stats stats_base; }; struct iocpt_dev_intf { @@ -313,6 +317,10 @@ typedef bool (*iocpt_cq_cb)(struct iocpt_cq *cq, uint16_t cq_desc_index, uint32_t iocpt_cq_service(struct iocpt_cq *cq, uint32_t work_to_do, iocpt_cq_cb cb, void *cb_arg); +void iocpt_get_stats(const struct iocpt_dev *dev, + struct rte_cryptodev_stats *stats); +void iocpt_reset_stats(struct iocpt_dev *dev); + static inline uint16_t iocpt_q_space_avail(struct iocpt_queue *q) { diff --git a/drivers/crypto/ionic/ionic_crypto_main.c b/drivers/crypto/ionic/ionic_crypto_main.c index 113347c57a..0685ddd457 100644 --- a/drivers/crypto/ionic/ionic_crypto_main.c +++ b/drivers/crypto/ionic/ionic_crypto_main.c @@ -128,6 +128,52 @@ iocpt_q_free(struct iocpt_queue *q) } } +static void +iocpt_get_abs_stats(const struct iocpt_dev *dev, + struct rte_cryptodev_stats *stats) +{ + uint32_t i; + + memset(stats, 0, sizeof(*stats)); + + /* Sum up the per-queue stats counters */ + for (i = 0; i < dev->crypto_dev->data->nb_queue_pairs; i++) { + struct rte_cryptodev_stats *q_stats = &dev->cryptoqs[i]->stats; + + stats->enqueued_count += q_stats->enqueued_count; + stats->dequeued_count += q_stats->dequeued_count; + stats->enqueue_err_count += q_stats->enqueue_err_count; + stats->dequeue_err_count += q_stats->dequeue_err_count; + } +} + +void +iocpt_get_stats(const struct iocpt_dev *dev, struct rte_cryptodev_stats *stats) +{ + /* Retrieve the new absolute stats values */ + iocpt_get_abs_stats(dev, stats); + + /* Subtract the base stats values to get relative values */ + stats->enqueued_count -= dev->stats_base.enqueued_count; + stats->dequeued_count -= dev->stats_base.dequeued_count; + stats->enqueue_err_count -= dev->stats_base.enqueue_err_count; + stats->dequeue_err_count -= dev->stats_base.dequeue_err_count; +} + +void +iocpt_reset_stats(struct iocpt_dev *dev) +{ + uint32_t i; + + /* Erase the per-queue stats counters */ + for (i = 0; i < dev->crypto_dev->data->nb_queue_pairs; i++) + memset(&dev->cryptoqs[i]->stats, 0, + sizeof(dev->cryptoqs[i]->stats)); + + /* Update the base stats values */ + iocpt_get_abs_stats(dev, &dev->stats_base); +} + static int iocpt_session_write(struct iocpt_session_priv *priv, enum iocpt_sess_control_oper oper) @@ -669,6 +715,8 @@ iocpt_init(struct iocpt_dev *dev) { int err; + memset(&dev->stats_base, 0, sizeof(dev->stats_base)); + /* Uses dev_cmds */ err = iocpt_dev_init(dev, dev->info_pa); if (err != 0) diff --git a/drivers/crypto/ionic/ionic_crypto_ops.c b/drivers/crypto/ionic/ionic_crypto_ops.c index 0330fd76ad..839bbf69d1 100644 --- a/drivers/crypto/ionic/ionic_crypto_ops.c +++ b/drivers/crypto/ionic/ionic_crypto_ops.c @@ -65,6 +65,23 @@ iocpt_op_info_get(struct rte_cryptodev *cdev, struct rte_cryptodev_info *info) info->min_mbuf_tailroom_req = 0; } +static void +iocpt_op_stats_get(struct rte_cryptodev *cdev, + struct rte_cryptodev_stats *stats) +{ + struct iocpt_dev *dev = cdev->data->dev_private; + + iocpt_get_stats(dev, stats); +} + +static void +iocpt_op_stats_reset(struct rte_cryptodev *cdev) +{ + struct iocpt_dev *dev = cdev->data->dev_private; + + iocpt_reset_stats(dev); +} + static int iocpt_op_queue_release(struct rte_cryptodev *cdev, uint16_t queue_id) { @@ -350,6 +367,7 @@ iocpt_enqueue_sym(void *qp, struct rte_crypto_op **ops, uint16_t nb_ops) struct iocpt_crypto_q *cptq = qp; struct rte_crypto_op *op; struct iocpt_session_priv *priv; + struct rte_cryptodev_stats *stats = &cptq->stats; uint16_t avail, count; int err; @@ -375,6 +393,7 @@ iocpt_enqueue_sym(void *qp, struct rte_crypto_op **ops, uint16_t nb_ops) err = iocpt_enq_one_aead(cptq, priv, op); if (unlikely(err != 0)) { op->status = RTE_CRYPTO_OP_STATUS_INVALID_ARGS; + stats->enqueue_err_count++; break; } @@ -386,6 +405,8 @@ iocpt_enqueue_sym(void *qp, struct rte_crypto_op **ops, uint16_t nb_ops) /* Restart timer if ops are being enqueued */ cptq->last_wdog_cycles = rte_get_timer_cycles(); + + stats->enqueued_count += count; } return count; @@ -439,8 +460,8 @@ iocpt_enqueue_wdog(struct iocpt_crypto_q *cptq) q->info[q->head_idx] = wdog_op; q->head_idx = Q_NEXT_TO_POST(q, 1); - IOCPT_PRINT(DEBUG, "Queue %u wdog enq %p", - q->index, wdog_op); + IOCPT_PRINT(DEBUG, "Queue %u wdog enq %p ops %"PRIu64, + q->index, wdog_op, cptq->stats.enqueued_count); cptq->enqueued_wdogs++; out_flush: @@ -456,6 +477,7 @@ iocpt_dequeue_sym(void *qp, struct rte_crypto_op **ops, uint16_t nb_ops) struct rte_crypto_op *op; struct iocpt_crypto_comp *cq_desc_base = cq->base; volatile struct iocpt_crypto_comp *cq_desc; + struct rte_cryptodev_stats *stats = &cptq->stats; uint64_t then, now, hz, delta; uint16_t count = 0; @@ -515,6 +537,9 @@ iocpt_dequeue_sym(void *qp, struct rte_crypto_op **ops, uint16_t nb_ops) continue; } + if (unlikely(op->status != RTE_CRYPTO_OP_STATUS_SUCCESS)) + stats->dequeue_err_count++; + ops[count] = op; q->info[q->tail_idx] = NULL; @@ -542,6 +567,8 @@ iocpt_dequeue_sym(void *qp, struct rte_crypto_op **ops, uint16_t nb_ops) /* Restart timer if the queue is making progress */ cptq->last_wdog_cycles = rte_get_timer_cycles(); + stats->dequeued_count += count; + return count; } @@ -552,6 +579,8 @@ static struct rte_cryptodev_ops iocpt_ops = { .dev_close = iocpt_op_close, .dev_infos_get = iocpt_op_info_get, + .stats_get = iocpt_op_stats_get, + .stats_reset = iocpt_op_stats_reset, .queue_pair_setup = iocpt_op_queue_setup, .queue_pair_release = iocpt_op_queue_release,