From patchwork Tue Apr 30 09:55:23 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Mattias_R=C3=B6nnblom?= X-Patchwork-Id: 139731 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 0340B43F3A; Tue, 30 Apr 2024 12:06:44 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id A1D01402F0; Tue, 30 Apr 2024 12:06:02 +0200 (CEST) Received: from EUR03-DBA-obe.outbound.protection.outlook.com (mail-dbaeur03on2061.outbound.protection.outlook.com [40.107.104.61]) by mails.dpdk.org (Postfix) with ESMTP id 33FBA402CC for ; Tue, 30 Apr 2024 12:05:58 +0200 (CEST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=Lza+C1LhbonjnCZ10BVzklX6ceS/wkoloV8oqH03u79IIbBghJa8Hi7IFgf1HlJK8T5SelwnaxSUYdgNUf7CN7PCr/HrnJO/YfEOFSpyXuD/ANGSF/wnYK3EkrYeAgdSEE0XwsUHnTg1ARjR+QGMfX6Ry5GYh8NueARbx/5VFphKSze+fYNguVzGxW5M5Gmi6N7W2oX2vU0kMGxdF1HtSQDKpAol5w0MblsDNL6pMGjdY/90DOZC6PaRD9V4E2obx1Q6CmuC23aXl+iVjqYOIFHoyIAwoJ05Ni/zZb3cuM2BwA+LO+H4+DMjX3pNLGooEAK4njuJui0z6kPdrZihjA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=0RozYixkAPZQJvhse9bVeHJcmbJm//9Hq35KyszlGRk=; b=YkA2E1LnZDHWjTlEhJ5FWRb2iX7MBndXk0XNMUYUc7X7KNP5bE5L6jLZ0jiBdA/nuevlsIkBYfYvCjLUWetUXYWyanUeD7VfwsBhk5yXHC17BWFGhZuHdYD+wbmYqzt2Qn6046onZ1ySUFO6l2E64/Jm3Uf1H6i5BtFfo4t4TESTroZ+PLE5ItHWNQ/ZufWu9q7p8nwoTGag1QP08Q76MneB1FfCvhIDhm0Rm0fj80CPKE824fPD+K/Wk+L61U8IIKccIhL6sp4d4YpAsH3Z3z/96xfl9VIjiAm39mouIrOAXtF5l5DgeVtMv8dWHqS0M4caxdFY9MHBnDK8PVpSig== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 192.176.1.74) smtp.rcpttodomain=dpdk.org smtp.mailfrom=ericsson.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=ericsson.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ericsson.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=0RozYixkAPZQJvhse9bVeHJcmbJm//9Hq35KyszlGRk=; b=YS+f29YKlk0JYUw4gpGpmX1+IyU2AAX1ev0XyDl++q5llRtMU3k1gLLYTq1qPSWTTJLO2nny+NfWAeFeSivTFfnsx3DIzlZi2Eh87HwvHMZKABfqLdx+1sFyxhP2VcOY/ROYLKtKb4KPSNblsu3ONuklAhhAPu6bi/oG5aGZ+jGL8Pkg3pYs2OCjWwWq2Tps7VS/j3VCrR5DhWV6hiVZDqnnSDtXC58Q1rT2wUk1gJF8XBLJoM6gilvjRew3mnZTaXC5zL7rS6pc5pp8tYcTnnrvqGmIm8oK8c4sv9pY6emRJxrPMez1HyGBq00q2lzEIqmsMSZ5ihrVGU4+nG/tkA== Received: from DUZP191CA0041.EURP191.PROD.OUTLOOK.COM (2603:10a6:10:4f8::20) by DBAPR07MB6502.eurprd07.prod.outlook.com (2603:10a6:10:188::10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7519.36; Tue, 30 Apr 2024 10:05:57 +0000 Received: from DB1PEPF000509F6.eurprd02.prod.outlook.com (2603:10a6:10:4f8:cafe::cf) by DUZP191CA0041.outlook.office365.com (2603:10a6:10:4f8::20) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7519.36 via Frontend Transport; Tue, 30 Apr 2024 10:05:57 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 192.176.1.74) smtp.mailfrom=ericsson.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=ericsson.com; Received-SPF: Pass (protection.outlook.com: domain of ericsson.com designates 192.176.1.74 as permitted sender) receiver=protection.outlook.com; client-ip=192.176.1.74; helo=oa.msg.ericsson.com; pr=C Received: from oa.msg.ericsson.com (192.176.1.74) by DB1PEPF000509F6.mail.protection.outlook.com (10.167.242.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7544.18 via Frontend Transport; Tue, 30 Apr 2024 10:05:56 +0000 Received: from seliicinfr00050.seli.gic.ericsson.se (153.88.142.248) by smtp-central.internal.ericsson.com (100.87.178.66) with Microsoft SMTP Server id 15.2.1544.9; Tue, 30 Apr 2024 12:05:55 +0200 Received: from breslau.. (seliicwb00002.seli.gic.ericsson.se [10.156.25.100]) by seliicinfr00050.seli.gic.ericsson.se (Postfix) with ESMTP id DCCAF1C006A; Tue, 30 Apr 2024 12:05:54 +0200 (CEST) From: =?utf-8?q?Mattias_R=C3=B6nnblom?= To: CC: , Heng Wang , "Stephen Hemminger" , Tyler Retzlaff , =?utf-8?q?Morten_Br=C3=B8rup?= , =?utf-8?q?Mattia?= =?utf-8?q?s_R=C3=B6nnblom?= Subject: [RFC v4 6/6] eal: add unit tests for atomic bit access functions Date: Tue, 30 Apr 2024 11:55:23 +0200 Message-ID: <20240430095523.108688-7-mattias.ronnblom@ericsson.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240430095523.108688-1-mattias.ronnblom@ericsson.com> References: <20240429095138.106849-2-mattias.ronnblom@ericsson.com> <20240430095523.108688-1-mattias.ronnblom@ericsson.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DB1PEPF000509F6:EE_|DBAPR07MB6502:EE_ X-MS-Office365-Filtering-Correlation-Id: 92a26675-b076-43d7-e2c8-08dc68fd2106 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230031|1800799015|36860700004|376005|82310400014; X-Microsoft-Antispam-Message-Info: =?utf-8?q?O8H39IEw4TP6ESn+0horXLGs1mzT9u7?= =?utf-8?q?xmdwenQzdylxOcUj6p4MiYc0WxjqX+ifIhIcxg0Sq3rA6yQUsp96B3p1gckurOCs3?= =?utf-8?q?lPUnaG4ViWAMoZNVSCz+lVI50+6ujnUXOKYVuPZnwc/moqoLJAxbX28rcquJwF3lj?= =?utf-8?q?nuvg6cLM1ymrufzuly35bHiTULklsGnhWJ7QAVeF3u5xinwC/eG0Y5YlJfhGyeuyy?= =?utf-8?q?66ki0FdxlV+HJFmTHoaljL4WoT4nDvXL0bCXuEKvjYFyHVQGqr/+goKuUbPtzs3gq?= =?utf-8?q?KQKMohKACy1C+7cCgefuqdnsc/TcKJBV91exqTPwVPGktAFJMghFdtX9s0lGqLbCF?= =?utf-8?q?04GvDQ/3bMe/qGfs4VR+o5Y0CItYbE0ewxhHq7Axpb/dEdCiPvP3eZ7awXKmv05Xs?= =?utf-8?q?v9kDlily7rpA3xatyb95E5M5MPOJGdfG2znYNQSRTfbqP3AK9/sXKkJwQGuLwnUcm?= =?utf-8?q?HeR/G6zw/e7C0ngjp64RwCuSAcUt60QX8V0OKUfErq7WcAYDEQuzeKWzObTBhQyEy?= =?utf-8?q?YiHZNY5va/pdOr+CvwJze0uOMKomnKCePrWInPMzILNEu8+ZVMl7LPA+CY2IbFmFi?= =?utf-8?q?qXhwre7IEkY/VGSWFUtL17JVdoNWvu3tQxyM58NqaECObJSP0NgR8qjbCqcYa/81l?= =?utf-8?q?75g5G6akVNYoSuq9+3cDm5F0M7azEef40kTaxe7YtkT1Ut8/CelIN4+wUU2yiLzga?= =?utf-8?q?jZg9+ULhrEB83Fb+fp471O9ZlWKEG4aMjN52hfJN0BHXu2tGUsBS2fHuTD6sPLCw3?= =?utf-8?q?6SQHIECve4rbuTuyw0mJZrbXDfHX9A1kNEf8T5JwHlGvRzpe8KQ9d5PD7tULIYz5j?= =?utf-8?q?Jb3YgfXrZbnuxGosgPqJNVige+5CfeZKIC7Pli21YoPz1cViRz3+sgYBu0m5JXZHj?= =?utf-8?q?xK+qiQus7UHLDnFPsX7z984iFTusM2tnHrzF8PAIYh6klLnTbpcmxy7hwbTbT+gEP?= =?utf-8?q?ZLdpAJ/AJaiASPa+uhZl+HCLFBx3YGEZVdVoWK0aoWoQQvYBdSfuyOvfX8H7IuLlw?= =?utf-8?q?ch7TRExcLja2rB29nZlOPF9r13YEg6PC9gPSYSC0T0WC1bj48Gl3CuEQQOuYzTuIR?= =?utf-8?q?TdXa5AJI3MDs+hZYnS5DsRM76LoECNEN+labp43n0OOtr9yseq7nAuCxkkBlEzhgq?= =?utf-8?q?KAj9vQpRQlPtWNADcNux2JzxipYANqhg0CQHC9L6QXJK4L20vqzQMnmOEm0rfq0Cn?= =?utf-8?q?t2XyzCJRtBmhNocR9irWFy01ASq+nrI/Mdfw/8qFmrAhTSMc3sqRC14eUV5e8hwOE?= =?utf-8?q?mc5Dph/5LitQthAqioOJd/ukDL9uduafTwMtA072frt+xmANxa5xDX5zZyUqmfbKG?= =?utf-8?q?Zn4VoYfKIOZ9?= X-Forefront-Antispam-Report: CIP:192.176.1.74; CTRY:SE; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:oa.msg.ericsson.com; PTR:office365.se.ericsson.net; CAT:NONE; SFS:(13230031)(1800799015)(36860700004)(376005)(82310400014); DIR:OUT; SFP:1101; X-OriginatorOrg: ericsson.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Apr 2024 10:05:56.8944 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 92a26675-b076-43d7-e2c8-08dc68fd2106 X-MS-Exchange-CrossTenant-Id: 92e84ceb-fbfd-47ab-be52-080c6b87953f X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=92e84ceb-fbfd-47ab-be52-080c6b87953f; Ip=[192.176.1.74]; Helo=[oa.msg.ericsson.com] X-MS-Exchange-CrossTenant-AuthSource: DB1PEPF000509F6.eurprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DBAPR07MB6502 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Extend bitops tests to cover the rte_bit_atomic_[set|clear|assign|test|test_and_[set|clear|assign]]() family of functions. RFC v4: * Add atomicity test for atomic bit flip. RFC v3: * Rename variable 'main' to make ICC happy. Signed-off-by: Mattias Rönnblom Acked-by: Morten Brørup Acked-by: Tyler Retzlaff --- app/test/test_bitops.c | 315 ++++++++++++++++++++++++++++++++++- lib/eal/include/rte_bitops.h | 1 - 2 files changed, 314 insertions(+), 2 deletions(-) diff --git a/app/test/test_bitops.c b/app/test/test_bitops.c index 615ec6e563..abc07e8caf 100644 --- a/app/test/test_bitops.c +++ b/app/test/test_bitops.c @@ -3,10 +3,13 @@ * Copyright(c) 2024 Ericsson AB */ +#include #include -#include #include +#include +#include +#include #include #include "test.h" @@ -64,6 +67,304 @@ GEN_TEST_BIT_ACCESS(test_bit_once_access64, rte_bit_once_set, rte_bit_once_clear, rte_bit_once_assign, rte_bit_once_flip, rte_bit_once_test, 64) +#define bit_atomic_set(addr, nr) \ + rte_bit_atomic_set(addr, nr, rte_memory_order_relaxed) + +#define bit_atomic_clear(addr, nr) \ + rte_bit_atomic_clear(addr, nr, rte_memory_order_relaxed) + +#define bit_atomic_assign(addr, nr, value) \ + rte_bit_atomic_assign(addr, nr, value, rte_memory_order_relaxed) + +#define bit_atomic_flip(addr, nr) \ + rte_bit_atomic_flip(addr, nr, rte_memory_order_relaxed) + +#define bit_atomic_test(addr, nr) \ + rte_bit_atomic_test(addr, nr, rte_memory_order_relaxed) + +GEN_TEST_BIT_ACCESS(test_bit_atomic_access32, bit_atomic_set, + bit_atomic_clear, bit_atomic_assign, + bit_atomic_flip, bit_atomic_test, 32) + +GEN_TEST_BIT_ACCESS(test_bit_atomic_access64, bit_atomic_set, + bit_atomic_clear, bit_atomic_assign, + bit_atomic_flip, bit_atomic_test, 64) + +#define PARALLEL_TEST_RUNTIME 0.25 + +#define GEN_TEST_BIT_PARALLEL_ASSIGN(size) \ + \ + struct parallel_access_lcore ## size \ + { \ + unsigned int bit; \ + uint ## size ##_t *word; \ + bool failed; \ + }; \ + \ + static int \ + run_parallel_assign ## size(void *arg) \ + { \ + struct parallel_access_lcore ## size *lcore = arg; \ + uint64_t deadline = rte_get_timer_cycles() + \ + PARALLEL_TEST_RUNTIME * rte_get_timer_hz(); \ + bool value = false; \ + \ + do { \ + bool new_value = rte_rand() & 1; \ + bool use_test_and_modify = rte_rand() & 1; \ + bool use_assign = rte_rand() & 1; \ + \ + if (rte_bit_atomic_test(lcore->word, lcore->bit, \ + rte_memory_order_relaxed) != value) { \ + lcore->failed = true; \ + break; \ + } \ + \ + if (use_test_and_modify) { \ + bool old_value; \ + if (use_assign) \ + old_value = rte_bit_atomic_test_and_assign( \ + lcore->word, lcore->bit, new_value, \ + rte_memory_order_relaxed); \ + else { \ + old_value = new_value ? \ + rte_bit_atomic_test_and_set( \ + lcore->word, lcore->bit, \ + rte_memory_order_relaxed) : \ + rte_bit_atomic_test_and_clear( \ + lcore->word, lcore->bit, \ + rte_memory_order_relaxed); \ + } \ + if (old_value != value) { \ + lcore->failed = true; \ + break; \ + } \ + } else { \ + if (use_assign) \ + rte_bit_atomic_assign(lcore->word, lcore->bit, \ + new_value, \ + rte_memory_order_relaxed); \ + else { \ + if (new_value) \ + rte_bit_atomic_set( \ + lcore->word, lcore->bit, \ + rte_memory_order_relaxed); \ + else \ + rte_bit_atomic_clear( \ + lcore->word, lcore->bit, \ + rte_memory_order_relaxed); \ + } \ + } \ + \ + value = new_value; \ + } while (rte_get_timer_cycles() < deadline); \ + \ + return 0; \ + } \ + \ + static int \ + test_bit_atomic_parallel_assign ## size(void) \ + { \ + unsigned int worker_lcore_id; \ + uint ## size ## _t word = 0; \ + struct parallel_access_lcore ## size lmain = { \ + .word = &word \ + }; \ + struct parallel_access_lcore ## size lworker = { \ + .word = &word \ + }; \ + \ + if (rte_lcore_count() < 2) { \ + printf("Need multiple cores to run parallel test.\n"); \ + return TEST_SKIPPED; \ + } \ + \ + worker_lcore_id = rte_get_next_lcore(-1, 1, 0); \ + \ + lmain.bit = rte_rand_max(size); \ + do { \ + lworker.bit = rte_rand_max(size); \ + } while (lworker.bit == lmain.bit); \ + \ + int rc = rte_eal_remote_launch(run_parallel_assign ## size, \ + &lworker, worker_lcore_id); \ + TEST_ASSERT(rc == 0, "Worker thread launch failed"); \ + \ + run_parallel_assign ## size(&lmain); \ + \ + rte_eal_mp_wait_lcore(); \ + \ + TEST_ASSERT(!lmain.failed, "Main lcore atomic access failed"); \ + TEST_ASSERT(!lworker.failed, "Worker lcore atomic access " \ + "failed"); \ + \ + return TEST_SUCCESS; \ + } + +GEN_TEST_BIT_PARALLEL_ASSIGN(32) +GEN_TEST_BIT_PARALLEL_ASSIGN(64) + +#define GEN_TEST_BIT_PARALLEL_TEST_AND_MODIFY(size) \ + \ + struct parallel_test_and_set_lcore ## size \ + { \ + uint ## size ##_t *word; \ + unsigned int bit; \ + uint64_t flips; \ + }; \ + \ + static int \ + run_parallel_test_and_modify ## size(void *arg) \ + { \ + struct parallel_test_and_set_lcore ## size *lcore = arg; \ + uint64_t deadline = rte_get_timer_cycles() + \ + PARALLEL_TEST_RUNTIME * rte_get_timer_hz(); \ + do { \ + bool old_value; \ + bool new_value = rte_rand() & 1; \ + bool use_assign = rte_rand() & 1; \ + \ + if (use_assign) \ + old_value = rte_bit_atomic_test_and_assign( \ + lcore->word, lcore->bit, new_value, \ + rte_memory_order_relaxed); \ + else \ + old_value = new_value ? \ + rte_bit_atomic_test_and_set( \ + lcore->word, lcore->bit, \ + rte_memory_order_relaxed) : \ + rte_bit_atomic_test_and_clear( \ + lcore->word, lcore->bit, \ + rte_memory_order_relaxed); \ + if (old_value != new_value) \ + lcore->flips++; \ + } while (rte_get_timer_cycles() < deadline); \ + \ + return 0; \ + } \ + \ + static int \ + test_bit_atomic_parallel_test_and_modify ## size(void) \ + { \ + unsigned int worker_lcore_id; \ + uint ## size ## _t word = 0; \ + unsigned int bit = rte_rand_max(size); \ + struct parallel_test_and_set_lcore ## size lmain = { \ + .word = &word, \ + .bit = bit \ + }; \ + struct parallel_test_and_set_lcore ## size lworker = { \ + .word = &word, \ + .bit = bit \ + }; \ + \ + if (rte_lcore_count() < 2) { \ + printf("Need multiple cores to run parallel test.\n"); \ + return TEST_SKIPPED; \ + } \ + \ + worker_lcore_id = rte_get_next_lcore(-1, 1, 0); \ + \ + int rc = rte_eal_remote_launch(run_parallel_test_and_modify ## size, \ + &lworker, worker_lcore_id); \ + TEST_ASSERT(rc == 0, "Worker thread launch failed"); \ + \ + run_parallel_test_and_modify ## size(&lmain); \ + \ + rte_eal_mp_wait_lcore(); \ + \ + uint64_t total_flips = lmain.flips + lworker.flips; \ + bool expected_value = total_flips % 2; \ + \ + TEST_ASSERT(expected_value == rte_bit_test(&word, bit), \ + "After %"PRId64" flips, the bit value " \ + "should be %d", total_flips, expected_value); \ + \ + uint64_t expected_word = 0; \ + rte_bit_assign(&expected_word, bit, expected_value); \ + \ + TEST_ASSERT(expected_word == word, "Untouched bits have " \ + "changed value"); \ + \ + return TEST_SUCCESS; \ + } + +GEN_TEST_BIT_PARALLEL_TEST_AND_MODIFY(32) +GEN_TEST_BIT_PARALLEL_TEST_AND_MODIFY(64) + +#define GEN_TEST_BIT_PARALLEL_FLIP(size) \ + \ + struct parallel_flip_lcore ## size \ + { \ + uint ## size ##_t *word; \ + unsigned int bit; \ + uint64_t flips; \ + }; \ + \ + static int \ + run_parallel_flip ## size(void *arg) \ + { \ + struct parallel_flip_lcore ## size *lcore = arg; \ + uint64_t deadline = rte_get_timer_cycles() + \ + PARALLEL_TEST_RUNTIME * rte_get_timer_hz(); \ + do { \ + rte_bit_atomic_flip(lcore->word, lcore->bit, \ + rte_memory_order_relaxed); \ + lcore->flips++; \ + } while (rte_get_timer_cycles() < deadline); \ + \ + return 0; \ + } \ + \ + static int \ + test_bit_atomic_parallel_flip ## size(void) \ + { \ + unsigned int worker_lcore_id; \ + uint ## size ## _t word = 0; \ + unsigned int bit = rte_rand_max(size); \ + struct parallel_flip_lcore ## size lmain = { \ + .word = &word, \ + .bit = bit \ + }; \ + struct parallel_flip_lcore ## size lworker = { \ + .word = &word, \ + .bit = bit \ + }; \ + \ + if (rte_lcore_count() < 2) { \ + printf("Need multiple cores to run parallel test.\n"); \ + return TEST_SKIPPED; \ + } \ + \ + worker_lcore_id = rte_get_next_lcore(-1, 1, 0); \ + \ + int rc = rte_eal_remote_launch(run_parallel_flip ## size, \ + &lworker, worker_lcore_id); \ + TEST_ASSERT(rc == 0, "Worker thread launch failed"); \ + \ + run_parallel_flip ## size(&lmain); \ + \ + rte_eal_mp_wait_lcore(); \ + \ + uint64_t total_flips = lmain.flips + lworker.flips; \ + bool expected_value = total_flips % 2; \ + \ + TEST_ASSERT(expected_value == rte_bit_test(&word, bit), \ + "After %"PRId64" flips, the bit value " \ + "should be %d", total_flips, expected_value); \ + \ + uint64_t expected_word = 0; \ + rte_bit_assign(&expected_word, bit, expected_value); \ + \ + TEST_ASSERT(expected_word == word, "Untouched bits have " \ + "changed value"); \ + \ + return TEST_SUCCESS; \ + } + +GEN_TEST_BIT_PARALLEL_FLIP(32) +GEN_TEST_BIT_PARALLEL_FLIP(64) + static uint32_t val32; static uint64_t val64; @@ -182,6 +483,18 @@ static struct unit_test_suite test_suite = { TEST_CASE(test_bit_access64), TEST_CASE(test_bit_once_access32), TEST_CASE(test_bit_once_access64), + TEST_CASE(test_bit_access32), + TEST_CASE(test_bit_access64), + TEST_CASE(test_bit_once_access32), + TEST_CASE(test_bit_once_access64), + TEST_CASE(test_bit_atomic_access32), + TEST_CASE(test_bit_atomic_access64), + TEST_CASE(test_bit_atomic_parallel_assign32), + TEST_CASE(test_bit_atomic_parallel_assign64), + TEST_CASE(test_bit_atomic_parallel_test_and_modify32), + TEST_CASE(test_bit_atomic_parallel_test_and_modify64), + TEST_CASE(test_bit_atomic_parallel_flip32), + TEST_CASE(test_bit_atomic_parallel_flip64), TEST_CASE(test_bit_relaxed_set), TEST_CASE(test_bit_relaxed_clear), TEST_CASE(test_bit_relaxed_test_set_clear), diff --git a/lib/eal/include/rte_bitops.h b/lib/eal/include/rte_bitops.h index f014bd913e..fb771c6dfc 100644 --- a/lib/eal/include/rte_bitops.h +++ b/lib/eal/include/rte_bitops.h @@ -560,7 +560,6 @@ extern "C" { uint32_t *: __rte_bit_atomic_test_and_clear32, \ uint64_t *: __rte_bit_atomic_test_and_clear64)(addr, nr, \ memory_order) - /** * @warning * @b EXPERIMENTAL: this API may change without prior notice.