From patchwork Fri Apr 19 06:43:15 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anoob Joseph X-Patchwork-Id: 139536 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 232F143EAC; Fri, 19 Apr 2024 08:43:45 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 919334067B; Fri, 19 Apr 2024 08:43:36 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id BD48E4067B for ; Fri, 19 Apr 2024 08:43:34 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.17.1.24/8.17.1.24) with ESMTP id 43ILYlnP010535; Thu, 18 Apr 2024 23:43:34 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:content-type; s= pfpt0220; bh=T7W4R3WQAcmYT0v5Sgs8JWFuRm5unoc8OuWUtlLLAh8=; b=bi3 IF+ewYH4KMjzF+G+NzEnUIUkIBH1cg9h25n8QHDIp4TaLy379er1Cmkmp9b6eQlA RXH5aRQzgWl6tWjlc77MF+9Xmrs+LgbqRopMp4ETHVtfBvEV2AFCBLAe16MBu03X ZPUV3vSVe+Kfl5rTDz7ESoAhrcysUzbTH0wU5rGyV0sfL6H73JmR5tG3n3APciG/ sFy5cecDFkHhtmfLTDwMLdTvbxen6NCo/VLlFuFzk7rRElG/GkqyZg4vpqWeXAGj ClCUH/835vX4G8KCZjjmR0AUDBFKUdIxMlLn5azbpvnybmaZmNWM8H3Vo7VWRz/o d1YlEuRInOEMYYXLKHA== Received: from dc5-exch05.marvell.com ([199.233.59.128]) by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3xjhecq8th-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 18 Apr 2024 23:43:33 -0700 (PDT) Received: from DC5-EXCH05.marvell.com (10.69.176.209) by DC5-EXCH05.marvell.com (10.69.176.209) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Thu, 18 Apr 2024 23:43:32 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH05.marvell.com (10.69.176.209) with Microsoft SMTP Server id 15.2.1544.4 via Frontend Transport; Thu, 18 Apr 2024 23:43:32 -0700 Received: from BG-LT92004.corp.innovium.com (BG-LT92004.marvell.com [10.28.163.189]) by maili.marvell.com (Postfix) with ESMTP id F3F625B6933; Thu, 18 Apr 2024 23:43:29 -0700 (PDT) From: Anoob Joseph To: Chengwen Feng , Kevin Laatz , Bruce Richardson , "Jerin Jacob" , Thomas Monjalon CC: Gowrishankar Muthukrishnan , "Vidya Sagar Velumuri" , Subject: [PATCH v3 3/7] dma/odm: add dev init and fini Date: Fri, 19 Apr 2024 12:13:15 +0530 Message-ID: <20240419064319.149-4-anoobj@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240419064319.149-1-anoobj@marvell.com> References: <20240417072708.322-1-anoobj@marvell.com> <20240419064319.149-1-anoobj@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: K29XywqRvd-EgDHnlTkktGUIk6_PdVp9 X-Proofpoint-GUID: K29XywqRvd-EgDHnlTkktGUIk6_PdVp9 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-04-19_04,2024-04-17_01,2023-05-22_02 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Gowrishankar Muthukrishnan Add ODM device init and fini. Signed-off-by: Anoob Joseph Signed-off-by: Gowrishankar Muthukrishnan Signed-off-by: Vidya Sagar Velumuri --- drivers/dma/odm/meson.build | 2 +- drivers/dma/odm/odm.c | 97 ++++++++++++++++++++++++++++++++++++ drivers/dma/odm/odm.h | 10 ++++ drivers/dma/odm/odm_dmadev.c | 13 +++++ 4 files changed, 121 insertions(+), 1 deletion(-) create mode 100644 drivers/dma/odm/odm.c diff --git a/drivers/dma/odm/meson.build b/drivers/dma/odm/meson.build index 227b10c890..d597762d37 100644 --- a/drivers/dma/odm/meson.build +++ b/drivers/dma/odm/meson.build @@ -9,6 +9,6 @@ endif deps += ['bus_pci', 'dmadev', 'eal', 'mempool', 'pci'] -sources = files('odm_dmadev.c') +sources = files('odm_dmadev.c', 'odm.c') pmd_supports_disable_iova_as_pa = true diff --git a/drivers/dma/odm/odm.c b/drivers/dma/odm/odm.c new file mode 100644 index 0000000000..c0963da451 --- /dev/null +++ b/drivers/dma/odm/odm.c @@ -0,0 +1,97 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2024 Marvell. + */ + +#include + +#include + +#include + +#include "odm.h" +#include "odm_priv.h" + +static void +odm_vchan_resc_free(struct odm_dev *odm, int qno) +{ + RTE_SET_USED(odm); + RTE_SET_USED(qno); +} + +static int +send_mbox_to_pf(struct odm_dev *odm, union odm_mbox_msg *msg, union odm_mbox_msg *rsp) +{ + int retry_cnt = ODM_MBOX_RETRY_CNT; + union odm_mbox_msg pf_msg; + + msg->d.err = ODM_MBOX_ERR_CODE_MAX; + odm_write64(msg->u[0], odm->rbase + ODM_MBOX_VF_PF_DATA(0)); + odm_write64(msg->u[1], odm->rbase + ODM_MBOX_VF_PF_DATA(1)); + + pf_msg.u[0] = 0; + pf_msg.u[1] = 0; + pf_msg.u[0] = odm_read64(odm->rbase + ODM_MBOX_VF_PF_DATA(0)); + + while (pf_msg.d.rsp == 0 && retry_cnt > 0) { + pf_msg.u[0] = odm_read64(odm->rbase + ODM_MBOX_VF_PF_DATA(0)); + --retry_cnt; + } + + if (retry_cnt <= 0) + return -EBADE; + + pf_msg.u[1] = odm_read64(odm->rbase + ODM_MBOX_VF_PF_DATA(1)); + + if (rsp) { + rsp->u[0] = pf_msg.u[0]; + rsp->u[1] = pf_msg.u[1]; + } + + if (pf_msg.d.rsp == msg->d.err && pf_msg.d.err != 0) + return -EBADE; + + return 0; +} + +int +odm_dev_init(struct odm_dev *odm) +{ + struct rte_pci_device *pci_dev = odm->pci_dev; + union odm_mbox_msg mbox_msg; + uint16_t vfid; + int rc; + + odm->rbase = pci_dev->mem_resource[0].addr; + vfid = ((pci_dev->addr.devid & 0x1F) << 3) | (pci_dev->addr.function & 0x7); + vfid -= 1; + odm->vfid = vfid; + odm->num_qs = 0; + + mbox_msg.u[0] = 0; + mbox_msg.u[1] = 0; + mbox_msg.q.vfid = odm->vfid; + mbox_msg.q.cmd = ODM_DEV_INIT; + rc = send_mbox_to_pf(odm, &mbox_msg, &mbox_msg); + if (!rc) + odm->max_qs = 1 << (4 - mbox_msg.d.nvfs); + + return rc; +} + +int +odm_dev_fini(struct odm_dev *odm) +{ + union odm_mbox_msg mbox_msg; + int qno, rc = 0; + + mbox_msg.u[0] = 0; + mbox_msg.u[1] = 0; + mbox_msg.q.vfid = odm->vfid; + mbox_msg.q.cmd = ODM_DEV_CLOSE; + rc = send_mbox_to_pf(odm, &mbox_msg, &mbox_msg); + + for (qno = 0; qno < odm->num_qs; qno++) + odm_vchan_resc_free(odm, qno); + + return rc; +} diff --git a/drivers/dma/odm/odm.h b/drivers/dma/odm/odm.h index 7564ffbed4..9fd3e30ad8 100644 --- a/drivers/dma/odm/odm.h +++ b/drivers/dma/odm/odm.h @@ -5,6 +5,10 @@ #ifndef _ODM_H_ #define _ODM_H_ +#include + +#include +#include #include extern int odm_logtype; @@ -50,6 +54,9 @@ extern int odm_logtype; #define ODM_MAX_QUEUES_PER_DEV 16 +#define odm_read64(addr) rte_read64_relaxed((volatile void *)(addr)) +#define odm_write64(val, addr) rte_write64_relaxed((val), (volatile void *)(addr)) + #define odm_err(...) \ rte_log(RTE_LOG_ERR, odm_logtype, \ RTE_FMT("%s(): %u" RTE_FMT_HEAD(__VA_ARGS__, ), __func__, __LINE__, \ @@ -142,4 +149,7 @@ struct __rte_cache_aligned odm_dev { uint8_t num_qs; }; +int odm_dev_init(struct odm_dev *odm); +int odm_dev_fini(struct odm_dev *odm); + #endif /* _ODM_H_ */ diff --git a/drivers/dma/odm/odm_dmadev.c b/drivers/dma/odm/odm_dmadev.c index cc3342cf7b..bef335c10c 100644 --- a/drivers/dma/odm/odm_dmadev.c +++ b/drivers/dma/odm/odm_dmadev.c @@ -23,6 +23,7 @@ odm_dmadev_probe(struct rte_pci_driver *pci_drv __rte_unused, struct rte_pci_dev char name[RTE_DEV_NAME_MAX_LEN]; struct odm_dev *odm = NULL; struct rte_dma_dev *dmadev; + int rc; if (!pci_dev->mem_resource[0].addr) return -ENODEV; @@ -37,8 +38,20 @@ odm_dmadev_probe(struct rte_pci_driver *pci_drv __rte_unused, struct rte_pci_dev } odm_info("DMA device %s probed", name); + odm = dmadev->data->dev_private; + + odm->pci_dev = pci_dev; + + rc = odm_dev_init(odm); + if (rc < 0) + goto dma_pmd_release; return 0; + +dma_pmd_release: + rte_dma_pmd_release(name); + + return rc; } static int