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Tue, 16 Apr 2024 08:31:06 -0700 From: Michael Baum To: CC: Matan Azrad , Dariusz Sosnowski , Raslan Darawsheh , Viacheslav Ovsiienko , Ori Kam , Suanming Mou , , Subject: [PATCH 2/4] net/mlx5/hws: fix GENEVE option class partial mask Date: Tue, 16 Apr 2024 18:30:52 +0300 Message-ID: <20240416153054.3216706-3-michaelba@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240416153054.3216706-1-michaelba@nvidia.com> References: <20240416153054.3216706-1-michaelba@nvidia.com> MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ5PEPF000001CD:EE_|SA1PR12MB8164:EE_ X-MS-Office365-Filtering-Correlation-Id: 507f3dbc-83ed-4455-79f5-08dc5e2a4f4a X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: loOG4c2Eb40kpZKvmUWq7nQmH/zglB73RfIwU847zvBIbfLQ8Xi0puD1N1TGWOvHraXPKgXAu6WAry3PAUh9kpS5S+ZWyEIuqxxIj19sknOmLdkuCAOyNR2UXpO+YVxk3Wm0R6sL+MsOvZK3qGHZquuEeLShyqTjIi9Od6NBD/Eu6O/9lbPep+lg0DAKKIbsIVo4GgOCV1Jk4OpiH/JQ2lE0DDlS/RQeT6cR4C20N6X39zN3lxwtLCxlNdjpK31ogPJmO57ymmHVjp59a+IW5bg7/992KoRdrJhYDesB6WWxj+5xmwT2gCxO+l6KqS6uSOdgIrcCBvFvB2L52S6jSwXN5hbefMPhE6ghv0+e+h5Fu3CP8jnzoRAFqyXBZxJQnQTyaZjyfPdeA0NgzPELrFEWEcwMbAb63IING5sytoXx55VbP5jcHDbAnDjxZ+kyEuGqrxL3NcYFyZrIn6eTgltP5CBEa+tZ2pcKxnGkHQwERVgUD/JqgRLiXwmXPM50CXdnI3Q3OBXI9B+StDmTPdXEAbuCk9XoUHk8SFCM5lFceOPAUS0MlbLblgveQ0dCYmij4g7a0dp1Ui4Cixx5FGmRIlHbcdtrAgFpE6FLwhHAfkkCR0UZTS4aVvNok//rsw/goJm/7REXZvnxlz2GsYLq+gjb1AyyGNg5koY9GSXYDfoV9ceF48AcvZwgWsZn01Y9K39KfQOLpEYM/xYx/pSvU3An/brRjNBaD3EyzZLPmxphH9KcNgIkVrUMREM4 X-Forefront-Antispam-Report: CIP:216.228.117.160; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge1.nvidia.com; CAT:NONE; SFS:(13230031)(36860700004)(1800799015)(82310400014)(376005); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Apr 2024 15:31:39.0436 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 507f3dbc-83ed-4455-79f5-08dc5e2a4f4a X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF000001CD.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR12MB8164 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org When GENEVE option parser is configured, the class field has 3 optional modes: 1. ignored - ignore this field. 2. fixed - this field is part of option identifier along with type field. In this mode, the exact value is provided in "spec" field during pattern template creation and mask must be 0xffff. 3. matchable - class field isn't part of the identifier and only mask is provided in pattern template creation. The mask can be any value like all other fields. In current implementation, when class mask isn't 0, pattern template creation is failed for mask != 0xffff regardless to class mode. This patch fixes this validation to be only when class mode is fixed. Fixes: 8f8dad4289e0 ("net/mlx5/hws: support GENEVE options matching") Cc: valex@nvidia.com Cc: stable@dpdk.org Signed-off-by: Michael Baum Reviewed-by: Alex Vesker --- drivers/net/mlx5/hws/mlx5dr_definer.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/net/mlx5/hws/mlx5dr_definer.c b/drivers/net/mlx5/hws/mlx5dr_definer.c index 35a2ed2048..f1f544deab 100644 --- a/drivers/net/mlx5/hws/mlx5dr_definer.c +++ b/drivers/net/mlx5/hws/mlx5dr_definer.c @@ -2500,11 +2500,6 @@ mlx5dr_definer_conv_item_geneve_opt(struct mlx5dr_definer_conv_data *cd, goto out_not_supp; } - if (m->option_class && m->option_class != RTE_BE16(UINT16_MAX)) { - DR_LOG(ERR, "Geneve option class has invalid mask"); - goto out_not_supp; - } - ret = mlx5_get_geneve_hl_data(cd->ctx, v->option_type, v->option_class, @@ -2517,6 +2512,11 @@ mlx5dr_definer_conv_item_geneve_opt(struct mlx5dr_definer_conv_data *cd, goto out_not_supp; } + if (ok_bit_on_class && m->option_class != RTE_BE16(UINT16_MAX)) { + DR_LOG(ERR, "Geneve option class has invalid mask"); + goto out_not_supp; + } + if (!ok_bit_on_class && m->option_class) { /* DW0 is used, we will match type, class */ if (!num_of_dws || hl_dws[0].dw_mask != UINT32_MAX) {