From patchwork Thu Apr 11 12:04:08 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: fengchengwen X-Patchwork-Id: 139231 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 9807543E44; Thu, 11 Apr 2024 14:06:23 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 233CE4029C; Thu, 11 Apr 2024 14:06:23 +0200 (CEST) Received: from szxga05-in.huawei.com (szxga05-in.huawei.com [45.249.212.191]) by mails.dpdk.org (Postfix) with ESMTP id EDA2840268 for ; Thu, 11 Apr 2024 14:06:20 +0200 (CEST) Received: from mail.maildlp.com (unknown [172.19.163.44]) by szxga05-in.huawei.com (SkyGuard) with ESMTP id 4VFddB4KqLz2NW5y; Thu, 11 Apr 2024 20:03:26 +0800 (CST) Received: from dggpeml500024.china.huawei.com (unknown [7.185.36.10]) by mail.maildlp.com (Postfix) with ESMTPS id 3E9FB1400C9; Thu, 11 Apr 2024 20:06:19 +0800 (CST) Received: from localhost.localdomain (10.50.165.33) by dggpeml500024.china.huawei.com (7.185.36.10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.1.2507.35; Thu, 11 Apr 2024 20:06:19 +0800 From: Chengwen Feng To: , CC: , , , , Subject: [PATCH v3] ethdev: fix strict aliasing lead to link cannot be up Date: Thu, 11 Apr 2024 12:04:08 +0000 Message-ID: <20240411120408.2397-1-fengchengwen@huawei.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20240411030749.41874-1-fengchengwen@huawei.com> References: <20240411030749.41874-1-fengchengwen@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.50.165.33] X-ClientProxiedBy: dggems706-chm.china.huawei.com (10.3.19.183) To dggpeml500024.china.huawei.com (7.185.36.10) X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Fix a problem introduced by a compiler upgrade (from gcc10 to gcc12.3), which will lead the hns3 NIC can't link up. The root cause is strict aliasing violation in rte_eth_linkstatus_set() with hns3 driver, see [1] for more details. This commit use union to avoid such aliasing violation. [1] Strict aliasing problem with rte_eth_linkstatus_set() https://marc.info/?l=dpdk-dev&m=171274148514777&w=3 Cc: stable@dpdk.org Signed-off-by: Chengwen Feng Signed-off-by: Dengdui Huang --- v3: fix checkpatch warning "missing --in-reply-to". v2: add RTE_ATOMIC(uint64_t) wrap which address Morten's comment. --- lib/ethdev/ethdev_driver.h | 23 +++++++---------------- lib/ethdev/rte_ethdev.h | 16 ++++++++++------ 2 files changed, 17 insertions(+), 22 deletions(-) diff --git a/lib/ethdev/ethdev_driver.h b/lib/ethdev/ethdev_driver.h index 0dbf2dd6a2..9d831d5c84 100644 --- a/lib/ethdev/ethdev_driver.h +++ b/lib/ethdev/ethdev_driver.h @@ -1674,18 +1674,13 @@ static inline int rte_eth_linkstatus_set(struct rte_eth_dev *dev, const struct rte_eth_link *new_link) { - RTE_ATOMIC(uint64_t) *dev_link = (uint64_t __rte_atomic *)&(dev->data->dev_link); - union { - uint64_t val64; - struct rte_eth_link link; - } orig; - - RTE_BUILD_BUG_ON(sizeof(*new_link) != sizeof(uint64_t)); + struct rte_eth_link old_link; - orig.val64 = rte_atomic_exchange_explicit(dev_link, *(const uint64_t *)new_link, - rte_memory_order_seq_cst); + old_link.val64 = rte_atomic_exchange_explicit(&dev->data->dev_link.val64, + new_link->val64, + rte_memory_order_seq_cst); - return (orig.link.link_status == new_link->link_status) ? -1 : 0; + return (old_link.link_status == new_link->link_status) ? -1 : 0; } /** @@ -1701,12 +1696,8 @@ static inline void rte_eth_linkstatus_get(const struct rte_eth_dev *dev, struct rte_eth_link *link) { - RTE_ATOMIC(uint64_t) *src = (uint64_t __rte_atomic *)&(dev->data->dev_link); - uint64_t *dst = (uint64_t *)link; - - RTE_BUILD_BUG_ON(sizeof(*link) != sizeof(uint64_t)); - - *dst = rte_atomic_load_explicit(src, rte_memory_order_seq_cst); + link->val64 = rte_atomic_load_explicit(&dev->data->dev_link.val64, + rte_memory_order_seq_cst); } /** diff --git a/lib/ethdev/rte_ethdev.h b/lib/ethdev/rte_ethdev.h index 147257d6a2..ccf43e468a 100644 --- a/lib/ethdev/rte_ethdev.h +++ b/lib/ethdev/rte_ethdev.h @@ -332,12 +332,16 @@ struct rte_eth_stats { /** * A structure used to retrieve link-level information of an Ethernet port. */ -__extension__ -struct __rte_aligned(8) rte_eth_link { /**< aligned for atomic64 read/write */ - uint32_t link_speed; /**< RTE_ETH_SPEED_NUM_ */ - uint16_t link_duplex : 1; /**< RTE_ETH_LINK_[HALF/FULL]_DUPLEX */ - uint16_t link_autoneg : 1; /**< RTE_ETH_LINK_[AUTONEG/FIXED] */ - uint16_t link_status : 1; /**< RTE_ETH_LINK_[DOWN/UP] */ +struct rte_eth_link { + union { + RTE_ATOMIC(uint64_t) val64; /**< used for atomic64 read/write */ + struct { + uint32_t link_speed; /**< RTE_ETH_SPEED_NUM_ */ + uint16_t link_duplex : 1; /**< RTE_ETH_LINK_[HALF/FULL]_DUPLEX */ + uint16_t link_autoneg : 1; /**< RTE_ETH_LINK_[AUTONEG/FIXED] */ + uint16_t link_status : 1; /**< RTE_ETH_LINK_[DOWN/UP] */ + }; + }; }; /**@{@name Link negotiation