From patchwork Wed Mar 27 18:44:13 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vladimir Medvedkin X-Patchwork-Id: 138872 X-Patchwork-Delegate: bruce.richardson@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id EE58A43CF0; Wed, 27 Mar 2024 19:44:21 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 87C88402B2; Wed, 27 Mar 2024 19:44:21 +0100 (CET) Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.19]) by mails.dpdk.org (Postfix) with ESMTP id 97CFA402A3; Wed, 27 Mar 2024 19:44:19 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1711565060; x=1743101060; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=zPFhn4n5ID10EcQYILkk6txchmK0PZ3izKmeQSYHryg=; b=nyCzhj0sbKQCZRhiT1qOOa8yYG+6gYueL1/tYaLhQmmTNwC+urURIIzA geeEPpVGvcToH9AFF84xp92BzFrXP4xHwJ2YHGnqMGI6Bf8CvYQfnOsIo HRQ0uTVmKCfma9Gy4XuUfTSkpIwbuLRe7q1UfWXfXdNrdCqhfIofBpH5S 2bFKF04Zt2gYX03JEHXyEeY+6G0vqQh/5nNVauWGoR9nOYzOdxlrGJLws y1GkD1EnBqYBka5H7bcavw4McoCBR025aI/whcmqRnYCkv0aTJWfiBqzy YNfPn7zjaAZOQDsxTlsSkvfMciMW+hMeulihobArVfgTh7sdqkN9iMUTJ g==; X-CSE-ConnectionGUID: NZ8jLzt/TmK6MmEIrWBHWw== X-CSE-MsgGUID: kSYHblK/Rxy9EAta332rnA== X-IronPort-AV: E=McAfee;i="6600,9927,11026"; a="6553098" X-IronPort-AV: E=Sophos;i="6.07,159,1708416000"; d="scan'208";a="6553098" Received: from orviesa010.jf.intel.com ([10.64.159.150]) by fmvoesa113.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Mar 2024 11:44:17 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,159,1708416000"; d="scan'208";a="16233068" Received: from silpixa00400072.ir.intel.com (HELO silpixa00400072.ger.corp.intel.com) ([10.237.222.194]) by orviesa010.jf.intel.com with ESMTP; 27 Mar 2024 11:44:16 -0700 From: Vladimir Medvedkin To: dev@dpdk.org Cc: david.marchand@redhat.com, carlosmn@weg.net, mingjinx.ye@intel.com, stable@dpdk.org Subject: [PATCH] net/ice: fix vlan stripping in double VLAN mode Date: Wed, 27 Mar 2024 18:44:13 +0000 Message-Id: <20240327184413.3192526-1-vladimir.medvedkin@intel.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org The ICE hardware can operate in two modes - single vlan mode or double vlan mode. Depending on the operating mode the hardware handles vlan header with single vlan tag differently. When double vlan enabled, a packet with a single VLAN is treated as a packet with outer VLAN only. Otherwise, a single VLAN in a packet is treated as inner VLAN. This patch fixes the logic of how vlan stripping is programmed. Bugzilla ID: 1402 Fixes: de5da9d16430 ("net/ice: support double VLAN") Cc: mingjinx.ye@intel.com Cc: stable@dpdk.org Signed-off-by: Vladimir Medvedkin Acked-by: Bruce Richardson --- drivers/net/ice/ice_ethdev.c | 45 +++++++++++++++++++++++++----------- 1 file changed, 32 insertions(+), 13 deletions(-) diff --git a/drivers/net/ice/ice_ethdev.c b/drivers/net/ice/ice_ethdev.c index 87385d2649..205c5f5f43 100644 --- a/drivers/net/ice/ice_ethdev.c +++ b/drivers/net/ice/ice_ethdev.c @@ -3826,7 +3826,10 @@ ice_dev_start(struct rte_eth_dev *dev) ice_set_tx_function(dev); mask = RTE_ETH_VLAN_STRIP_MASK | RTE_ETH_VLAN_FILTER_MASK | - RTE_ETH_VLAN_EXTEND_MASK | RTE_ETH_QINQ_STRIP_MASK; + RTE_ETH_VLAN_EXTEND_MASK; + if (ice_is_dvm_ena(hw)) + mask |= RTE_ETH_QINQ_STRIP_MASK; + ret = ice_vlan_offload_set(dev, mask); if (ret) { PMD_INIT_LOG(ERR, "Unable to set VLAN offload"); @@ -4896,19 +4899,35 @@ ice_vlan_offload_set(struct rte_eth_dev *dev, int mask) ice_vsi_config_vlan_filter(vsi, false); } - if (mask & RTE_ETH_VLAN_STRIP_MASK) { - if (rxmode->offloads & RTE_ETH_RX_OFFLOAD_VLAN_STRIP) - ice_vsi_config_vlan_stripping(vsi, true); - else - ice_vsi_config_vlan_stripping(vsi, false); - } + struct ice_hw *hw = ICE_VSI_TO_HW(vsi); + if (!ice_is_dvm_ena(hw)) { + if (mask & RTE_ETH_VLAN_STRIP_MASK) { + if (rxmode->offloads & RTE_ETH_RX_OFFLOAD_VLAN_STRIP) + ice_vsi_config_vlan_stripping(vsi, true); + else + ice_vsi_config_vlan_stripping(vsi, false); + } - if (mask & RTE_ETH_QINQ_STRIP_MASK) { - /* Enable or disable outer VLAN stripping */ - if (rxmode->offloads & RTE_ETH_RX_OFFLOAD_QINQ_STRIP) - ice_vsi_config_outer_vlan_stripping(vsi, true); - else - ice_vsi_config_outer_vlan_stripping(vsi, false); + if (mask & RTE_ETH_QINQ_STRIP_MASK) { + PMD_DRV_LOG(ERR, "Single VLAN mode (SVM) does not support qinq"); + return -ENOTSUP; + } + } else { + if ((mask & RTE_ETH_VLAN_STRIP_MASK) | + (mask & RTE_ETH_QINQ_STRIP_MASK)) { + if (rxmode->offloads & (RTE_ETH_RX_OFFLOAD_VLAN_STRIP | + RTE_ETH_RX_OFFLOAD_QINQ_STRIP)) + ice_vsi_config_outer_vlan_stripping(vsi, true); + else + ice_vsi_config_outer_vlan_stripping(vsi, false); + } + + if (mask & RTE_ETH_QINQ_STRIP_MASK) { + if (rxmode->offloads & RTE_ETH_RX_OFFLOAD_QINQ_STRIP) + ice_vsi_config_vlan_stripping(vsi, true); + else + ice_vsi_config_vlan_stripping(vsi, false); + } } return 0;