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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by BL6PEPF0001AB75.mail.protection.outlook.com (10.167.242.168) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.7409.10 via Frontend Transport; Thu, 21 Mar 2024 18:48:35 +0000 Received: from ubuntu2004.linuxvmimages.local (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Thu, 21 Mar 2024 13:48:32 -0500 From: Sivaprasad Tummala To: , , , , , , , , , , CC: , Subject: [PATCH v6 06/14] examples/l3fwd-power: fix lcore ID restriction Date: Thu, 21 Mar 2024 19:47:12 +0100 Message-ID: <20240321184721.69040-7-sivaprasad.tummala@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240321184721.69040-1-sivaprasad.tummala@amd.com> References: <20240318173146.24303-1-sivaprasad.tummala@amd.com> <20240321184721.69040-1-sivaprasad.tummala@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL6PEPF0001AB75:EE_|MW6PR12MB9000:EE_ X-MS-Office365-Filtering-Correlation-Id: a38e83a0-e6ce-4b6c-3d71-08dc49d783f8 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 Mar 2024 18:48:35.9710 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a38e83a0-e6ce-4b6c-3d71-08dc49d783f8 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF0001AB75.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW6PR12MB9000 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Currently the config option allows lcore IDs up to 255, irrespective of RTE_MAX_LCORES and needs to be fixed. The patch fixes these constraints by allowing all lcore IDs up to RTE_MAX_LCORES. Fixes: f88e7c175a68 ("examples/l3fwd-power: add high/regular perf cores options") Cc: radu.nicolau@intel.com Cc: stable@dpdk.org Signed-off-by: Sivaprasad Tummala Acked-by: Morten Brørup Acked-by: Ferruh Yigit --- examples/l3fwd-power/main.c | 14 +++++++------- examples/l3fwd-power/main.h | 2 +- examples/l3fwd-power/perf_core.c | 6 +++--- 3 files changed, 11 insertions(+), 11 deletions(-) diff --git a/examples/l3fwd-power/main.c b/examples/l3fwd-power/main.c index 1881b1b194..5411592dca 100644 --- a/examples/l3fwd-power/main.c +++ b/examples/l3fwd-power/main.c @@ -1397,7 +1397,7 @@ static int check_lcore_params(void) { uint16_t queue, i; - uint8_t lcore; + uint32_t lcore; int socketid; for (i = 0; i < nb_lcore_params; ++i) { @@ -1408,13 +1408,13 @@ check_lcore_params(void) } lcore = lcore_params[i].lcore_id; if (!rte_lcore_is_enabled(lcore)) { - printf("error: lcore %hhu is not enabled in lcore " + printf("error: lcore %u is not enabled in lcore " "mask\n", lcore); return -1; } if ((socketid = rte_lcore_to_socket_id(lcore) != 0) && (numa_on == 0)) { - printf("warning: lcore %hhu is on socket %d with numa " + printf("warning: lcore %u is on socket %d with numa " "off\n", lcore, socketid); } if (app_mode == APP_MODE_TELEMETRY && lcore == rte_lcore_id()) { @@ -1466,14 +1466,14 @@ static int init_lcore_rx_queues(void) { uint16_t i, nb_rx_queue; - uint8_t lcore; + uint32_t lcore; for (i = 0; i < nb_lcore_params; ++i) { lcore = lcore_params[i].lcore_id; nb_rx_queue = lcore_conf[lcore].n_rx_queue; if (nb_rx_queue >= MAX_RX_QUEUE_PER_LCORE) { printf("error: too many queues (%u) for lcore: %u\n", - (unsigned)nb_rx_queue + 1, (unsigned)lcore); + (unsigned int)nb_rx_queue + 1, lcore); return -1; } else { lcore_conf[lcore].rx_queue_list[nb_rx_queue].port_id = @@ -1659,7 +1659,7 @@ parse_config(const char *q_arg) int i; unsigned size; unsigned int max_fld[_NUM_FLD] = {USHRT_MAX, - USHRT_MAX, UCHAR_MAX}; + USHRT_MAX, RTE_MAX_LCORE}; nb_lcore_params = 0; @@ -1693,7 +1693,7 @@ parse_config(const char *q_arg) lcore_params_array[nb_lcore_params].queue_id = (uint16_t)int_fld[FLD_QUEUE]; lcore_params_array[nb_lcore_params].lcore_id = - (uint8_t)int_fld[FLD_LCORE]; + (uint32_t)int_fld[FLD_LCORE]; ++nb_lcore_params; } lcore_params = lcore_params_array; diff --git a/examples/l3fwd-power/main.h b/examples/l3fwd-power/main.h index 40b5194726..194bd82102 100644 --- a/examples/l3fwd-power/main.h +++ b/examples/l3fwd-power/main.h @@ -10,7 +10,7 @@ struct lcore_params { uint16_t port_id; uint16_t queue_id; - uint8_t lcore_id; + uint32_t lcore_id; } __rte_cache_aligned; extern struct lcore_params *lcore_params; diff --git a/examples/l3fwd-power/perf_core.c b/examples/l3fwd-power/perf_core.c index 3088935ee0..d8b35d062c 100644 --- a/examples/l3fwd-power/perf_core.c +++ b/examples/l3fwd-power/perf_core.c @@ -24,7 +24,7 @@ struct perf_lcore_params { uint16_t port_id; uint16_t queue_id; uint8_t high_perf; - uint8_t lcore_idx; + uint32_t lcore_idx; } __rte_cache_aligned; static struct perf_lcore_params prf_lc_prms[MAX_LCORE_PARAMS]; @@ -133,7 +133,7 @@ parse_perf_config(const char *q_arg) int i; unsigned int size; unsigned int max_fld[_NUM_FLD] = {USHRT_MAX, USHRT_MAX, - UCHAR_MAX, UCHAR_MAX}; + UCHAR_MAX, RTE_MAX_LCORE}; nb_prf_lc_prms = 0; @@ -171,7 +171,7 @@ parse_perf_config(const char *q_arg) prf_lc_prms[nb_prf_lc_prms].high_perf = !!(uint8_t)int_fld[FLD_LCORE_HP]; prf_lc_prms[nb_prf_lc_prms].lcore_idx = - (uint8_t)int_fld[FLD_LCORE_IDX]; + (uint32_t)int_fld[FLD_LCORE_IDX]; ++nb_prf_lc_prms; }