From patchwork Thu Mar 14 13:18:36 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vidya Sagar Velumuri X-Patchwork-Id: 138402 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 966AE43CA6; Thu, 14 Mar 2024 14:21:22 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 7C27C42EBA; Thu, 14 Mar 2024 14:21:07 +0100 (CET) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id 1DEBB42EAF for ; Thu, 14 Mar 2024 14:21:04 +0100 (CET) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.17.1.24/8.17.1.24) with ESMTP id 42E5JM17011236 for ; Thu, 14 Mar 2024 06:21:04 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:content-type; s= pfpt0220; bh=7oRSPuDB0eGuElgCCjn0vKSVxBzJ1Q50mn4HnG77qP8=; b=ONC WYl/xsieum1qCHyPQg0mKrH9Fe18VLk/GQhG2rOQSjQ+CbYiRKIZzDi6xEI5HUB1 5x/HwJi5Nj6pDHxBJ5yxN8toobXBzn/Fa4Zuz7NhG2rLHpJoV0Vc+BytLDp716+E uNvRRvNqaoXhn4zJL255SG1soB4rGqqGT1TZAbWwVt8m3MSC6TGCuHxVXIPrjoGi se0G/zhdm8sEgvOBerHW5vHXwhztl2opNTfwNIHr05XktqLoHb9vCVxDP4bINtC7 /NZtzxgB50AeDs85avbxpHiDL7KyH6qLNfwaapTr2Snj1WpMqqOxMOd0ZiqNu3Dm MqbIxFfLDSIQuaoETcQ== Received: from dc6wp-exch02.marvell.com ([4.21.29.225]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3wutyq9q6b-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT) for ; Thu, 14 Mar 2024 06:21:04 -0700 (PDT) Received: from DC6WP-EXCH02.marvell.com (10.76.176.209) by DC6WP-EXCH02.marvell.com (10.76.176.209) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.12; Thu, 14 Mar 2024 06:21:03 -0700 Received: from maili.marvell.com (10.69.176.80) by DC6WP-EXCH02.marvell.com (10.76.176.209) with Microsoft SMTP Server id 15.2.1258.12 via Frontend Transport; Thu, 14 Mar 2024 06:21:03 -0700 Received: from localhost.localdomain (unknown [10.28.36.179]) by maili.marvell.com (Postfix) with ESMTP id 462405B6928; Thu, 14 Mar 2024 06:21:00 -0700 (PDT) From: Vidya Sagar Velumuri To: Ankur Dwivedi , Anoob Joseph , Tejasree Kondoj CC: , , , , Subject: [PATCH v2 5/8] crypto/cnxk: move metadata to second cacheline Date: Thu, 14 Mar 2024 06:18:36 -0700 Message-ID: <20240314131839.3362494-6-vvelumuri@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240314083844.3319506-1-vvelumuri@marvell.com> References: <20240314083844.3319506-1-vvelumuri@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: DD3ceY8TmxL5hbEqAfXUTnhcJ7gvMuc_ X-Proofpoint-ORIG-GUID: DD3ceY8TmxL5hbEqAfXUTnhcJ7gvMuc_ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-03-14_11,2024-03-13_01,2023-05-22_02 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org In security session, move PMD metadata to second cacheline. Also optimize the fields to minimize the memory usage. Signed-off-by: Anoob Joseph Signed-off-by: Vidya Sagar Velumuri --- drivers/crypto/cnxk/cn10k_cryptodev_sec.h | 10 ++++++---- drivers/crypto/cnxk/cn10k_ipsec.c | 4 ++-- drivers/crypto/cnxk/cn10k_tls.c | 2 +- 3 files changed, 9 insertions(+), 7 deletions(-) diff --git a/drivers/crypto/cnxk/cn10k_cryptodev_sec.h b/drivers/crypto/cnxk/cn10k_cryptodev_sec.h index 881a0276cc..230c0f7c1c 100644 --- a/drivers/crypto/cnxk/cn10k_cryptodev_sec.h +++ b/drivers/crypto/cnxk/cn10k_cryptodev_sec.h @@ -5,6 +5,7 @@ #ifndef __CN10K_CRYPTODEV_SEC_H__ #define __CN10K_CRYPTODEV_SEC_H__ +#include #include #include "roc_constants.h" @@ -19,23 +20,24 @@ struct cn10k_sec_session { uint8_t rte_sess[SEC_SESS_SIZE]; /** PMD private space */ + RTE_MARKER cacheline1 __rte_cache_aligned; - enum rte_security_session_protocol proto; /** Pre-populated CPT inst words */ struct cnxk_cpt_inst_tmpl inst; uint16_t max_extended_len; uint16_t iv_offset; + uint8_t proto; uint8_t iv_length; union { struct { uint8_t ip_csum; - bool is_outbound; + uint8_t is_outbound : 1; } ipsec; struct { uint8_t enable_padding : 1; uint8_t tail_fetch_len : 2; - uint8_t rvsd : 5; - bool is_write; + uint8_t is_write : 1; + uint8_t rvsd : 4; } tls; }; /** Queue pair */ diff --git a/drivers/crypto/cnxk/cn10k_ipsec.c b/drivers/crypto/cnxk/cn10k_ipsec.c index 74d6cd70d1..ef5f0ff4aa 100644 --- a/drivers/crypto/cnxk/cn10k_ipsec.c +++ b/drivers/crypto/cnxk/cn10k_ipsec.c @@ -76,7 +76,7 @@ cn10k_ipsec_outb_sa_create(struct roc_cpt *roc_cpt, struct roc_cpt_lf *lf, } #endif - sec_sess->ipsec.is_outbound = true; + sec_sess->ipsec.is_outbound = 1; /* Get Rlen calculation data */ ret = cnxk_ipsec_outb_rlens_get(&rlens, ipsec_xfrm, crypto_xfrm); @@ -177,7 +177,7 @@ cn10k_ipsec_inb_sa_create(struct roc_cpt *roc_cpt, struct roc_cpt_lf *lf, goto sa_dptr_free; } - sec_sess->ipsec.is_outbound = false; + sec_sess->ipsec.is_outbound = 0; sec_sess->inst.w7 = cpt_inst_w7_get(roc_cpt, in_sa); /* Save index/SPI in cookie, specific required for Rx Inject */ diff --git a/drivers/crypto/cnxk/cn10k_tls.c b/drivers/crypto/cnxk/cn10k_tls.c index 11279dac46..ae3ed3176c 100644 --- a/drivers/crypto/cnxk/cn10k_tls.c +++ b/drivers/crypto/cnxk/cn10k_tls.c @@ -739,7 +739,7 @@ cn10k_tls_write_sa_create(struct roc_cpt *roc_cpt, struct roc_cpt_lf *lf, sec_sess->iv_length = crypto_xfrm->next->cipher.iv.length; } - sec_sess->tls.is_write = true; + sec_sess->tls.is_write = 1; sec_sess->tls.enable_padding = tls_xfrm->options.extra_padding_enable; sec_sess->max_extended_len = tls_write_rlens_get(tls_xfrm, crypto_xfrm); sec_sess->proto = RTE_SECURITY_PROTOCOL_TLS_RECORD;