diff mbox series

common/qat: fix undefined macro

Message ID 20240305115537.3042539-1-ciara.power@intel.com (mailing list archive)
State Accepted, archived
Delegated to: akhil goyal
Headers
Series common/qat: fix undefined macro |

Checks

Context Check Description
ci/checkpatch success coding style OK
ci/loongarch-compilation success Compilation OK
ci/loongarch-unit-testing success Unit Testing PASS
ci/Intel-compilation success Compilation OK
ci/intel-Testing success Testing PASS
ci/github-robot: build success github build: passed
ci/intel-Functional success Functional PASS
ci/iol-intel-Performance success Performance Testing PASS
ci/iol-intel-Functional success Functional Testing PASS
ci/iol-mellanox-Performance success Performance Testing PASS
ci/iol-abi-testing success Testing PASS
ci/iol-compile-amd64-testing success Testing PASS
ci/iol-unit-amd64-testing success Testing PASS
ci/iol-unit-arm64-testing success Testing PASS
ci/iol-compile-arm64-testing success Testing PASS
ci/iol-broadcom-Performance success Performance Testing PASS
ci/iol-sample-apps-testing success Testing PASS
ci/iol-broadcom-Functional success Functional Testing PASS

Commit Message

Power, Ciara March 5, 2024, 11:55 a.m. UTC 
  When using RTE_ENABLE_ASSERT and debug mode, an undefined
macro error appeared for ICP_QAT_FW_SYM_COMM_ADDR_SGL.
This was not being defined, but is now added to the header file.

Bugzilla ID: 1395
Fixes: e9271821e489 ("common/qat: support GEN LCE device")

Signed-off-by: Ciara Power <ciara.power@intel.com>

---
Cc: nishikanta.nayak@intel.com
---
 drivers/common/qat/qat_adf/icp_qat_fw_la.h | 1 +
 1 file changed, 1 insertion(+)

Comments

Nayak, Nishikanta March 5, 2024, 12:08 p.m. UTC | #1 
> -----Original Message-----
> From: Power, Ciara <ciara.power@intel.com>
> Sent: Tuesday, March 5, 2024 5:26 PM
> To: dev@dpdk.org
> Cc: gakhil@marvell.com; Power, Ciara <ciara.power@intel.com>; Nayak,
> Nishikanta <nishikanta.nayak@intel.com>; Ji, Kai <kai.ji@intel.com>
> Subject: [PATCH] common/qat: fix undefined macro
> 
> When using RTE_ENABLE_ASSERT and debug mode, an undefined macro
> error appeared for ICP_QAT_FW_SYM_COMM_ADDR_SGL.
> This was not being defined, but is now added to the header file.
> 
> Bugzilla ID: 1395
> Fixes: e9271821e489 ("common/qat: support GEN LCE device")
> 
> Signed-off-by: Ciara Power <ciara.power@intel.com>
> 
> ---
> Cc: nishikanta.nayak@intel.com
> ---
>  drivers/common/qat/qat_adf/icp_qat_fw_la.h | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/drivers/common/qat/qat_adf/icp_qat_fw_la.h
> b/drivers/common/qat/qat_adf/icp_qat_fw_la.h
> index 67fc25c919..fe32b66c50 100644
> --- a/drivers/common/qat/qat_adf/icp_qat_fw_la.h
> +++ b/drivers/common/qat/qat_adf/icp_qat_fw_la.h
> @@ -111,6 +111,7 @@ struct icp_qat_fw_la_bulk_req {  #define
> ICP_QAT_FW_SYM_IV_IN_DESC_VALID 1  #define
> ICP_QAT_FW_SYM_DIRECTION_BITPOS 15  #define
> ICP_QAT_FW_SYM_DIRECTION_MASK 0x1
> +#define ICP_QAT_FW_SYM_COMM_ADDR_SGL 1
> 
>  /* In GEN_LCE AEAD AES GCM Algorithm has ID 0 */  #define
> QAT_LA_CRYPTO_AEAD_AES_GCM_GEN_LCE 0
> --
> 2.25.1

Acked-by: Nishikant Nayak <nishikanta.nayak@intel.com>
Ali Alnubani March 5, 2024, 12:15 p.m. UTC | #2 
> -----Original Message-----
> From: Ciara Power <ciara.power@intel.com>
> Sent: Tuesday, March 5, 2024 1:56 PM
> To: dev@dpdk.org
> Cc: gakhil@marvell.com; Ciara Power <ciara.power@intel.com>;
> nishikanta.nayak@intel.com; Kai Ji <kai.ji@intel.com>
> Subject: [PATCH] common/qat: fix undefined macro
> 
> When using RTE_ENABLE_ASSERT and debug mode, an undefined
> macro error appeared for ICP_QAT_FW_SYM_COMM_ADDR_SGL.
> This was not being defined, but is now added to the header file.
> 
> Bugzilla ID: 1395
> Fixes: e9271821e489 ("common/qat: support GEN LCE device")
> 
> Signed-off-by: Ciara Power <ciara.power@intel.com>
> 
> ---

Can confirm it resolves the build failure, thanks!

Tested-by: Ali Alnubani <alialnu@nvidia.com>
Thomas Monjalon March 5, 2024, 1:17 p.m. UTC | #3 
05/03/2024 13:15, Ali Alnubani:
> > -----Original Message-----
> > From: Ciara Power <ciara.power@intel.com>
> > Sent: Tuesday, March 5, 2024 1:56 PM
> > To: dev@dpdk.org
> > Cc: gakhil@marvell.com; Ciara Power <ciara.power@intel.com>;
> > nishikanta.nayak@intel.com; Kai Ji <kai.ji@intel.com>
> > Subject: [PATCH] common/qat: fix undefined macro
> > 
> > When using RTE_ENABLE_ASSERT and debug mode, an undefined
> > macro error appeared for ICP_QAT_FW_SYM_COMM_ADDR_SGL.
> > This was not being defined, but is now added to the header file.
> > 
> > Bugzilla ID: 1395
> > Fixes: e9271821e489 ("common/qat: support GEN LCE device")
> > 
> > Signed-off-by: Ciara Power <ciara.power@intel.com>
> > 
> > ---
> 
> Can confirm it resolves the build failure, thanks!
> 
> Tested-by: Ali Alnubani <alialnu@nvidia.com>

Reported-by: Ali Alnubani <alialnu@nvidia.com>

Applied, thanks.
diff mbox series

Patch

diff --git a/drivers/common/qat/qat_adf/icp_qat_fw_la.h b/drivers/common/qat/qat_adf/icp_qat_fw_la.h
index 67fc25c919..fe32b66c50 100644
--- a/drivers/common/qat/qat_adf/icp_qat_fw_la.h
+++ b/drivers/common/qat/qat_adf/icp_qat_fw_la.h
@@ -111,6 +111,7 @@  struct icp_qat_fw_la_bulk_req {
 #define ICP_QAT_FW_SYM_IV_IN_DESC_VALID 1
 #define ICP_QAT_FW_SYM_DIRECTION_BITPOS 15
 #define ICP_QAT_FW_SYM_DIRECTION_MASK 0x1
+#define ICP_QAT_FW_SYM_COMM_ADDR_SGL 1
 
 /* In GEN_LCE AEAD AES GCM Algorithm has ID 0 */
 #define QAT_LA_CRYPTO_AEAD_AES_GCM_GEN_LCE 0