diff --git a/doc/guides/rel_notes/release_24_03.rst b/doc/guides/rel_notes/release_24_03.rst
index dc498a29ce..0ba9b3c569 100644
--- a/doc/guides/rel_notes/release_24_03.rst
+++ b/doc/guides/rel_notes/release_24_03.rst
@@ -146,6 +146,10 @@ New Features
     to support TLS v1.2, TLS v1.3 and DTLS v1.2.
   * Added PMD API to allow raw submission of instructions to CPT.
 
+* **Updated Intel QuickAssist Technology driver.**
+
+  * Enabled support for virtual QAT - vQAT (0da5) devices in QAT PMD.
+
 
 Removed Items
 -------------
diff --git a/drivers/common/qat/dev/qat_dev_gen4.c b/drivers/common/qat/dev/qat_dev_gen4.c
index 2525e1e695..b7a6321e79 100644
--- a/drivers/common/qat/dev/qat_dev_gen4.c
+++ b/drivers/common/qat/dev/qat_dev_gen4.c
@@ -144,6 +144,42 @@ qat_dev_read_config_gen4(struct qat_pci_device *qat_dev)
 	return 0;
 }
 
+static int
+qat_dev_read_config_vqat(struct qat_pci_device *qat_dev)
+{
+	int i = 0;
+	struct qat_dev_gen4_extra *dev_extra = qat_dev->dev_private;
+	struct qat_qp_hw_data *hw_data;
+	struct qat_device_info *qat_dev_instance =
+			&qat_pci_devs[qat_dev->qat_dev_id];
+	uint16_t sub_id = qat_dev_instance->pci_dev->id.subsystem_device_id;
+
+	for (; i < QAT_GEN4_BUNDLE_NUM; i++) {
+		hw_data = &dev_extra->qp_gen4_data[i][0];
+		memset(hw_data, 0, sizeof(*hw_data));
+		if (sub_id == ADF_VQAT_SYM_PCI_SUBSYSTEM_ID) {
+			hw_data->service_type = QAT_SERVICE_SYMMETRIC;
+			hw_data->tx_msg_size = 128;
+			hw_data->rx_msg_size = 32;
+		} else if (sub_id == ADF_VQAT_ASYM_PCI_SUBSYSTEM_ID) {
+			hw_data->service_type = QAT_SERVICE_ASYMMETRIC;
+			hw_data->tx_msg_size = 64;
+			hw_data->rx_msg_size = 32;
+		} else if (sub_id == ADF_VQAT_DC_PCI_SUBSYSTEM_ID) {
+			hw_data->service_type = QAT_SERVICE_COMPRESSION;
+			hw_data->tx_msg_size = 128;
+			hw_data->rx_msg_size = 32;
+		} else {
+			QAT_LOG(ERR, "Unrecognized subsystem id %hu", sub_id);
+			return -EINVAL;
+		}
+		hw_data->tx_ring_num = 0;
+		hw_data->rx_ring_num = 1;
+		hw_data->hw_bundle_num = i;
+	}
+	return 0;
+}
+
 void
 qat_qp_build_ring_base_gen4(void *io_addr,
 			struct qat_queue *queue)
@@ -269,6 +305,12 @@ qat_reset_ring_pairs_gen4(struct qat_pci_device *qat_pci_dev)
 	return 0;
 }
 
+static int
+qat_reset_ring_pairs_vqat(struct qat_pci_device *qat_pci_dev __rte_unused)
+{
+	return 0;
+}
+
 const struct rte_mem_resource *
 qat_dev_get_transport_bar_gen4(struct rte_pci_device *pci_dev)
 {
@@ -305,10 +347,21 @@ static struct qat_dev_hw_spec_funcs qat_dev_hw_spec_gen4 = {
 	.qat_dev_get_slice_map = qat_dev_get_slice_map_gen4,
 };
 
+static struct qat_dev_hw_spec_funcs qat_dev_hw_spec_vqat = {
+	.qat_dev_reset_ring_pairs = qat_reset_ring_pairs_vqat,
+	.qat_dev_get_transport_bar = qat_dev_get_transport_bar_gen4,
+	.qat_dev_get_misc_bar = qat_dev_get_misc_bar_gen4,
+	.qat_dev_read_config = qat_dev_read_config_vqat,
+	.qat_dev_get_extra_size = qat_dev_get_extra_size_gen4,
+	.qat_dev_get_slice_map = qat_dev_get_slice_map_gen4,
+};
+
 RTE_INIT(qat_dev_gen_4_init)
 {
-	qat_qp_hw_spec[QAT_GEN4] = &qat_qp_hw_spec_gen4;
+	qat_qp_hw_spec[QAT_VQAT] = qat_qp_hw_spec[QAT_GEN4] = &qat_qp_hw_spec_gen4;
 	qat_dev_hw_spec[QAT_GEN4] = &qat_dev_hw_spec_gen4;
+	qat_dev_hw_spec[QAT_VQAT] = &qat_dev_hw_spec_vqat;
 	qat_gen_config[QAT_GEN4].dev_gen = QAT_GEN4;
+	qat_gen_config[QAT_VQAT].dev_gen = QAT_VQAT;
 	qat_gen_config[QAT_GEN4].pf2vf_dev = &qat_pf2vf_gen4;
 }
diff --git a/drivers/common/qat/qat_adf/icp_qat_hw.h b/drivers/common/qat/qat_adf/icp_qat_hw.h
index b99dde2176..21ee3cf8fd 100644
--- a/drivers/common/qat/qat_adf/icp_qat_hw.h
+++ b/drivers/common/qat/qat_adf/icp_qat_hw.h
@@ -9,6 +9,11 @@
 #define ADF_C4XXXIOV_VFLEGFUSES_OFFSET	0x4C
 #define ADF1_C4XXXIOV_VFLEGFUSES_LEN	4
 
+/* Definition of virtual QAT subsystem ID*/
+#define ADF_VQAT_SYM_PCI_SUBSYSTEM_ID 0x00
+#define ADF_VQAT_ASYM_PCI_SUBSYSTEM_ID 0x01
+#define ADF_VQAT_DC_PCI_SUBSYSTEM_ID 0x02
+
 enum icp_qat_slice_mask {
 	ICP_ACCEL_MASK_CIPHER_SLICE = 0x01,
 	ICP_ACCEL_MASK_AUTH_SLICE = 0x02,
diff --git a/drivers/common/qat/qat_common.h b/drivers/common/qat/qat_common.h
index 44a8dff802..12f281e5b1 100644
--- a/drivers/common/qat/qat_common.h
+++ b/drivers/common/qat/qat_common.h
@@ -23,6 +23,7 @@ enum qat_device_gen {
 	QAT_GEN4,
 	QAT_GEN5,
 	QAT_GEN_LCE,
+	QAT_VQAT,
 	QAT_N_GENS
 };
 
diff --git a/drivers/common/qat/qat_device.c b/drivers/common/qat/qat_device.c
index a77c628256..09347845e0 100644
--- a/drivers/common/qat/qat_device.c
+++ b/drivers/common/qat/qat_device.c
@@ -71,6 +71,9 @@ static const struct rte_pci_id pci_id_qat_map[] = {
 		{
 			RTE_PCI_DEVICE(0x8086, 0x1454),
 		},
+		{
+			RTE_PCI_DEVICE(0x8086, 0x0da5),
+		},
 		{.device_id = 0},
 };
 
@@ -213,6 +216,8 @@ pick_gen(const struct rte_pci_device *pci_dev)
 		return QAT_GEN5;
 	case 0x1454:
 		return QAT_GEN_LCE;
+	case 0x0da5:
+		return QAT_VQAT;
 	default:
 		QAT_LOG(ERR, "Invalid dev_id, can't determine generation");
 		return QAT_N_GENS;
@@ -302,6 +307,7 @@ qat_pci_device_allocate(struct rte_pci_device *pci_dev,
 	strlcpy(qat_dev->name, name, QAT_DEV_NAME_MAX_LEN);
 	qat_dev->qat_dev_id = qat_dev_id;
 	qat_dev->qat_dev_gen = qat_dev_gen;
+	qat_pci_devs[qat_dev_id].pci_dev = pci_dev;
 
 	if (wireless_slice_support(pci_dev->id.device_id))
 		qat_dev->has_wireless_slice = 1;
@@ -350,7 +356,6 @@ qat_pci_device_allocate(struct rte_pci_device *pci_dev,
 	 * qat_dev to list of devices
 	 */
 	qat_pci_devs[qat_dev_id].mz = qat_dev_mz;
-	qat_pci_devs[qat_dev_id].pci_dev = pci_dev;
 	qat_nb_pci_devices++;
 
 	QAT_LOG(DEBUG, "QAT device %d found, name %s, total QATs %d",
diff --git a/drivers/compress/qat/dev/qat_comp_pmd_gen4.c b/drivers/compress/qat/dev/qat_comp_pmd_gen4.c
index 68d111e07c..f177ba2309 100644
--- a/drivers/compress/qat/dev/qat_comp_pmd_gen4.c
+++ b/drivers/compress/qat/dev/qat_comp_pmd_gen4.c
@@ -198,16 +198,22 @@ qat_comp_get_num_im_bufs_required_gen4(void)
 
 RTE_INIT(qat_comp_pmd_gen4_init)
 {
-	qat_comp_gen_dev_ops[QAT_GEN4].compressdev_ops =
+	qat_comp_gen_dev_ops[QAT_VQAT].compressdev_ops =
+		qat_comp_gen_dev_ops[QAT_GEN4].compressdev_ops =
 			&qat_comp_ops_gen4;
-	qat_comp_gen_dev_ops[QAT_GEN4].qat_comp_get_capabilities =
+	qat_comp_gen_dev_ops[QAT_VQAT].qat_comp_get_capabilities =
+		qat_comp_gen_dev_ops[QAT_GEN4].qat_comp_get_capabilities =
 			qat_comp_cap_get_gen4;
-	qat_comp_gen_dev_ops[QAT_GEN4].qat_comp_get_num_im_bufs_required =
+	qat_comp_gen_dev_ops[QAT_VQAT].qat_comp_get_num_im_bufs_required =
+		qat_comp_gen_dev_ops[QAT_GEN4].qat_comp_get_num_im_bufs_required =
 			qat_comp_get_num_im_bufs_required_gen4;
-	qat_comp_gen_dev_ops[QAT_GEN4].qat_comp_get_ram_bank_flags =
+	qat_comp_gen_dev_ops[QAT_VQAT].qat_comp_get_ram_bank_flags =
+		qat_comp_gen_dev_ops[QAT_GEN4].qat_comp_get_ram_bank_flags =
 			qat_comp_get_ram_bank_flags_gen4;
-	qat_comp_gen_dev_ops[QAT_GEN4].qat_comp_set_slice_cfg_word =
+	qat_comp_gen_dev_ops[QAT_VQAT].qat_comp_set_slice_cfg_word =
+		qat_comp_gen_dev_ops[QAT_GEN4].qat_comp_set_slice_cfg_word =
 			qat_comp_set_slice_cfg_word_gen4;
-	qat_comp_gen_dev_ops[QAT_GEN4].qat_comp_get_feature_flags =
+	qat_comp_gen_dev_ops[QAT_VQAT].qat_comp_get_feature_flags =
+		qat_comp_gen_dev_ops[QAT_GEN4].qat_comp_get_feature_flags =
 			qat_comp_get_features_gen1;
 }
diff --git a/drivers/compress/qat/qat_comp_pmd.c b/drivers/compress/qat/qat_comp_pmd.c
index 6fb8cf69be..815276fc9e 100644
--- a/drivers/compress/qat/qat_comp_pmd.c
+++ b/drivers/compress/qat/qat_comp_pmd.c
@@ -682,11 +682,18 @@ qat_comp_dev_create(struct qat_pci_device *qat_pci_dev,
 	const struct qat_comp_gen_dev_ops *qat_comp_gen_ops =
 			&qat_comp_gen_dev_ops[qat_pci_dev->qat_dev_gen];
 	uint64_t capa_size;
+	uint16_t sub_id = qat_dev_instance->pci_dev->id.subsystem_device_id;
 
 	snprintf(name, RTE_COMPRESSDEV_NAME_MAX_LEN, "%s_%s",
 			qat_pci_dev->name, "comp");
 	QAT_LOG(DEBUG, "Creating QAT COMP device %s", name);
 
+	if (qat_pci_dev->qat_dev_gen == QAT_VQAT &&
+		sub_id != ADF_VQAT_DC_PCI_SUBSYSTEM_ID) {
+		QAT_LOG(ERR, "Device (vqat instance) %s does not support compression",
+				name);
+		return -EFAULT;
+	}
 	if (qat_comp_gen_ops->compressdev_ops == NULL) {
 		QAT_LOG(DEBUG, "Device %s does not support compression", name);
 		return -ENOTSUP;
diff --git a/drivers/crypto/qat/dev/qat_crypto_pmd_gen4.c b/drivers/crypto/qat/dev/qat_crypto_pmd_gen4.c
index 9c7f7d98c8..11f6078759 100644
--- a/drivers/crypto/qat/dev/qat_crypto_pmd_gen4.c
+++ b/drivers/crypto/qat/dev/qat_crypto_pmd_gen4.c
@@ -406,14 +406,18 @@ qat_sym_configure_raw_dp_ctx_gen4(void *_raw_dp_ctx, void *_ctx)
 
 RTE_INIT(qat_sym_crypto_gen4_init)
 {
-	qat_sym_gen_dev_ops[QAT_GEN4].cryptodev_ops = &qat_sym_crypto_ops_gen1;
-	qat_sym_gen_dev_ops[QAT_GEN4].get_capabilities =
+	qat_sym_gen_dev_ops[QAT_VQAT].cryptodev_ops =
+		qat_sym_gen_dev_ops[QAT_GEN4].cryptodev_ops = &qat_sym_crypto_ops_gen1;
+	qat_sym_gen_dev_ops[QAT_VQAT].get_capabilities =
+		qat_sym_gen_dev_ops[QAT_GEN4].get_capabilities =
 			qat_sym_crypto_cap_get_gen4;
-	qat_sym_gen_dev_ops[QAT_GEN4].set_session =
+	qat_sym_gen_dev_ops[QAT_VQAT].set_session =
+		qat_sym_gen_dev_ops[QAT_GEN4].set_session =
 			qat_sym_crypto_set_session_gen4;
 	qat_sym_gen_dev_ops[QAT_GEN4].set_raw_dp_ctx =
 			qat_sym_configure_raw_dp_ctx_gen4;
-	qat_sym_gen_dev_ops[QAT_GEN4].get_feature_flags =
+	qat_sym_gen_dev_ops[QAT_VQAT].get_feature_flags =
+		qat_sym_gen_dev_ops[QAT_GEN4].get_feature_flags =
 			qat_sym_crypto_feature_flags_get_gen1;
 	qat_sym_gen_dev_ops[QAT_GEN4].create_security_ctx =
 			qat_sym_create_security_gen1;
@@ -421,12 +425,16 @@ RTE_INIT(qat_sym_crypto_gen4_init)
 
 RTE_INIT(qat_asym_crypto_gen4_init)
 {
-	qat_asym_gen_dev_ops[QAT_GEN4].cryptodev_ops =
+	qat_asym_gen_dev_ops[QAT_VQAT].cryptodev_ops =
+		qat_asym_gen_dev_ops[QAT_GEN4].cryptodev_ops =
 			&qat_asym_crypto_ops_gen1;
-	qat_asym_gen_dev_ops[QAT_GEN4].get_capabilities =
+	qat_asym_gen_dev_ops[QAT_VQAT].get_capabilities =
+		qat_asym_gen_dev_ops[QAT_GEN4].get_capabilities =
 			qat_asym_crypto_cap_get_gen1;
-	qat_asym_gen_dev_ops[QAT_GEN4].get_feature_flags =
+	qat_asym_gen_dev_ops[QAT_VQAT].get_feature_flags =
+		qat_asym_gen_dev_ops[QAT_GEN4].get_feature_flags =
 			qat_asym_crypto_feature_flags_get_gen1;
-	qat_asym_gen_dev_ops[QAT_GEN4].set_session =
+	qat_asym_gen_dev_ops[QAT_VQAT].set_session =
+		qat_asym_gen_dev_ops[QAT_GEN4].set_session =
 			qat_asym_crypto_set_session_gen1;
 }
diff --git a/drivers/crypto/qat/qat_asym.c b/drivers/crypto/qat/qat_asym.c
index 2bf3060278..d96eb7ec6d 100644
--- a/drivers/crypto/qat/qat_asym.c
+++ b/drivers/crypto/qat/qat_asym.c
@@ -1517,11 +1517,18 @@ qat_asym_dev_create(struct qat_pci_device *qat_pci_dev,
 	char capa_memz_name[RTE_CRYPTODEV_NAME_MAX_LEN];
 	int i = 0;
 	uint16_t slice_map = 0;
+	uint16_t sub_id = qat_dev_instance->pci_dev->id.subsystem_device_id;
 
 	snprintf(name, RTE_CRYPTODEV_NAME_MAX_LEN, "%s_%s",
 			qat_pci_dev->name, "asym");
 	QAT_LOG(DEBUG, "Creating QAT ASYM device %s\n", name);
 
+	if (qat_pci_dev->qat_dev_gen == QAT_VQAT &&
+		sub_id != ADF_VQAT_ASYM_PCI_SUBSYSTEM_ID) {
+		QAT_LOG(ERR, "Device (vqat instance) %s does not support asymmetric crypto",
+				name);
+		return -EFAULT;
+	}
 	if (gen_dev_ops->cryptodev_ops == NULL) {
 		QAT_LOG(ERR, "Device %s does not support asymmetric crypto",
 				name);
diff --git a/drivers/crypto/qat/qat_sym.c b/drivers/crypto/qat/qat_sym.c
index 9113dfef56..3bf6ce8a75 100644
--- a/drivers/crypto/qat/qat_sym.c
+++ b/drivers/crypto/qat/qat_sym.c
@@ -209,11 +209,18 @@ qat_sym_dev_create(struct qat_pci_device *qat_pci_dev,
 	enum qat_device_gen qat_dev_gen = qat_pci_dev->qat_dev_gen;
 	const struct qat_crypto_gen_dev_ops *gen_dev_ops =
 		&qat_sym_gen_dev_ops[qat_pci_dev->qat_dev_gen];
+	uint16_t sub_id = qat_dev_instance->pci_dev->id.subsystem_device_id;
 
 	snprintf(name, RTE_CRYPTODEV_NAME_MAX_LEN, "%s_%s",
 			qat_pci_dev->name, "sym");
 	QAT_LOG(DEBUG, "Creating QAT SYM device %s", name);
 
+	if (qat_pci_dev->qat_dev_gen == QAT_VQAT &&
+		sub_id != ADF_VQAT_SYM_PCI_SUBSYSTEM_ID) {
+		QAT_LOG(ERR, "Device (vqat instance) %s does not support symmetric crypto",
+				name);
+		return -EFAULT;
+	}
 	if (gen_dev_ops->cryptodev_ops == NULL) {
 		QAT_LOG(ERR, "Device %s does not support symmetric crypto",
 				name);
diff --git a/drivers/crypto/qat/qat_sym_session.c b/drivers/crypto/qat/qat_sym_session.c
index e763cfcb51..9e2dba5423 100644
--- a/drivers/crypto/qat/qat_sym_session.c
+++ b/drivers/crypto/qat/qat_sym_session.c
@@ -410,7 +410,8 @@ qat_sym_session_configure_cipher(struct rte_cryptodev *dev,
 			goto error_out;
 		}
 		session->qat_mode = ICP_QAT_HW_CIPHER_CTR_MODE;
-		if (qat_dev_gen == QAT_GEN4 || qat_dev_gen == QAT_GEN5)
+		if (qat_dev_gen == QAT_GEN4 || qat_dev_gen == QAT_GEN5 ||
+				qat_dev_gen == QAT_VQAT)
 			session->is_ucs = 1;
 		break;
 	case RTE_CRYPTO_CIPHER_SNOW3G_UEA2:
@@ -959,7 +960,8 @@ qat_sym_session_configure_auth(struct rte_cryptodev *dev,
 			session->auth_iv.length = AES_GCM_J0_LEN;
 		else
 			session->is_iv12B = 1;
-		if (qat_dev_gen == QAT_GEN4 || qat_dev_gen == QAT_GEN5) {
+		if (qat_dev_gen == QAT_GEN4 || qat_dev_gen == QAT_GEN5 ||
+				qat_dev_gen == QAT_VQAT) {
 			session->is_cnt_zero = 1;
 			session->is_ucs = 1;
 		}
@@ -1141,7 +1143,8 @@ qat_sym_session_configure_aead(struct rte_cryptodev *dev,
 		session->qat_mode = ICP_QAT_HW_CIPHER_CTR_MODE;
 		session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_GALOIS_128;
 
-		if (qat_dev_gen == QAT_GEN4 || qat_dev_gen == QAT_GEN5)
+		if (qat_dev_gen == QAT_GEN4 || qat_dev_gen == QAT_GEN5 ||
+				qat_dev_gen == QAT_VQAT)
 			session->is_ucs = 1;
 		if (session->cipher_iv.length == 0) {
 			session->cipher_iv.length = AES_GCM_J0_LEN;
@@ -1161,13 +1164,15 @@ qat_sym_session_configure_aead(struct rte_cryptodev *dev,
 		}
 		session->qat_mode = ICP_QAT_HW_CIPHER_CTR_MODE;
 		session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_AES_CBC_MAC;
-		if (qat_dev_gen == QAT_GEN4 || qat_dev_gen == QAT_GEN5)
+		if (qat_dev_gen == QAT_GEN4 || qat_dev_gen == QAT_GEN5 ||
+				qat_dev_gen == QAT_VQAT)
 			session->is_ucs = 1;
 		break;
 	case RTE_CRYPTO_AEAD_CHACHA20_POLY1305:
 		if (aead_xform->key.length != ICP_QAT_HW_CHACHAPOLY_KEY_SZ)
 			return -EINVAL;
-		if (qat_dev_gen == QAT_GEN4 || qat_dev_gen == QAT_GEN5)
+		if (qat_dev_gen == QAT_GEN4 || qat_dev_gen == QAT_GEN5 ||
+				qat_dev_gen == QAT_VQAT)
 			session->is_ucs = 1;
 		session->qat_cipher_alg =
 				ICP_QAT_HW_CIPHER_ALGO_CHACHA20_POLY1305;
@@ -2469,7 +2474,8 @@ int qat_sym_cd_auth_set(struct qat_sym_session *cdesc,
 		auth_param->u2.inner_prefix_sz =
 			qat_hash_get_block_size(cdesc->qat_hash_alg);
 		auth_param->hash_state_sz = digestsize;
-		if (qat_dev_gen == QAT_GEN4 || qat_dev_gen == QAT_GEN5) {
+		if (qat_dev_gen == QAT_GEN4 || qat_dev_gen == QAT_GEN5 ||
+				qat_dev_gen == QAT_VQAT) {
 			ICP_QAT_FW_HASH_FLAG_MODE2_SET(
 				hash_cd_ctrl->hash_flags,
 				QAT_FW_LA_MODE2);
