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dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.160 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.160; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.160) by SN1PEPF0002BA51.mail.protection.outlook.com (10.167.242.74) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7292.25 via Frontend Transport; Tue, 13 Feb 2024 13:50:44 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.66) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.41; Tue, 13 Feb 2024 05:50:30 -0800 Received: from nvidia.com (10.126.230.35) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.12; Tue, 13 Feb 2024 05:50:27 -0800 From: Ori Kam To: , , , , , Viacheslav Ovsiienko , Suanming Mou , Matan Azrad CC: , , Subject: [PATCH v3 3/4] net/mlx5: add calc encap hash support Date: Tue, 13 Feb 2024 15:48:32 +0200 Message-ID: <20240213134834.16762-3-orika@nvidia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240213134834.16762-1-orika@nvidia.com> References: <20240128093943.4461-1-orika@nvidia.com> <20240213134834.16762-1-orika@nvidia.com> MIME-Version: 1.0 X-Originating-IP: [10.126.230.35] X-ClientProxiedBy: rnnvmail203.nvidia.com (10.129.68.9) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF0002BA51:EE_|CH3PR12MB8187:EE_ X-MS-Office365-Filtering-Correlation-Id: 6d38684f-149a-4ad0-1aef-08dc2c9ac686 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Feb 2024 13:50:44.5624 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 6d38684f-149a-4ad0-1aef-08dc2c9ac686 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF0002BA51.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR12MB8187 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org This commit adds support for encap hash calculation. Signed-off-by: Ori Kam Acked-by: Dariusz Sosnowski --- drivers/net/mlx5/mlx5_flow.c | 29 +++++++++++++++ drivers/net/mlx5/mlx5_flow.h | 8 ++++ drivers/net/mlx5/mlx5_flow_hw.c | 66 +++++++++++++++++++++++++++++++++ 3 files changed, 103 insertions(+) diff --git a/drivers/net/mlx5/mlx5_flow.c b/drivers/net/mlx5/mlx5_flow.c index 40376c99ba..7c5a5da8ec 100644 --- a/drivers/net/mlx5/mlx5_flow.c +++ b/drivers/net/mlx5/mlx5_flow.c @@ -1197,6 +1197,12 @@ mlx5_flow_calc_table_hash(struct rte_eth_dev *dev, const struct rte_flow_item pattern[], uint8_t pattern_template_index, uint32_t *hash, struct rte_flow_error *error); +static int +mlx5_flow_calc_encap_hash(struct rte_eth_dev *dev, + const struct rte_flow_item pattern[], + enum rte_flow_encap_hash_field dest_field, + uint8_t *hash, + struct rte_flow_error *error); static const struct rte_flow_ops mlx5_flow_ops = { .validate = mlx5_flow_validate, @@ -1253,6 +1259,7 @@ static const struct rte_flow_ops mlx5_flow_ops = { .async_action_list_handle_query_update = mlx5_flow_async_action_list_handle_query_update, .flow_calc_table_hash = mlx5_flow_calc_table_hash, + .flow_calc_encap_hash = mlx5_flow_calc_encap_hash, }; /* Tunnel information. */ @@ -11121,6 +11128,28 @@ mlx5_flow_calc_table_hash(struct rte_eth_dev *dev, hash, error); } +static int +mlx5_flow_calc_encap_hash(struct rte_eth_dev *dev, + const struct rte_flow_item pattern[], + enum rte_flow_encap_hash_field dest_field, + uint8_t *hash, + struct rte_flow_error *error) +{ + enum mlx5_flow_drv_type drv_type = flow_get_drv_type(dev, NULL); + const struct mlx5_flow_driver_ops *fops; + + if (drv_type == MLX5_FLOW_TYPE_MIN || drv_type == MLX5_FLOW_TYPE_MAX) + return rte_flow_error_set(error, ENOTSUP, + RTE_FLOW_ERROR_TYPE_ACTION, + NULL, "invalid driver type"); + fops = flow_get_drv_ops(drv_type); + if (!fops || !fops->flow_calc_encap_hash) + return rte_flow_error_set(error, ENOTSUP, + RTE_FLOW_ERROR_TYPE_ACTION, + NULL, "no calc encap hash handler"); + return fops->flow_calc_encap_hash(dev, pattern, dest_field, hash, error); +} + /** * Destroy all indirect actions (shared RSS). * diff --git a/drivers/net/mlx5/mlx5_flow.h b/drivers/net/mlx5/mlx5_flow.h index b086dfaf28..a4d0ff7b13 100644 --- a/drivers/net/mlx5/mlx5_flow.h +++ b/drivers/net/mlx5/mlx5_flow.h @@ -2198,6 +2198,13 @@ typedef int const struct rte_flow_item pattern[], uint8_t pattern_template_index, uint32_t *hash, struct rte_flow_error *error); +typedef int +(*mlx5_flow_calc_encap_hash_t) + (struct rte_eth_dev *dev, + const struct rte_flow_item pattern[], + enum rte_flow_encap_hash_field dest_field, + uint8_t *hash, + struct rte_flow_error *error); struct mlx5_flow_driver_ops { mlx5_flow_validate_t validate; @@ -2271,6 +2278,7 @@ struct mlx5_flow_driver_ops { mlx5_flow_async_action_list_handle_query_update_t async_action_list_handle_query_update; mlx5_flow_calc_table_hash_t flow_calc_table_hash; + mlx5_flow_calc_encap_hash_t flow_calc_encap_hash; }; /* mlx5_flow.c */ diff --git a/drivers/net/mlx5/mlx5_flow_hw.c b/drivers/net/mlx5/mlx5_flow_hw.c index 3af5e1f160..ce2fb7c5f9 100644 --- a/drivers/net/mlx5/mlx5_flow_hw.c +++ b/drivers/net/mlx5/mlx5_flow_hw.c @@ -11701,6 +11701,71 @@ flow_hw_calc_table_hash(struct rte_eth_dev *dev, return 0; } +static int +flow_hw_calc_encap_hash(struct rte_eth_dev *dev, + const struct rte_flow_item pattern[], + enum rte_flow_encap_hash_field dest_field, + uint8_t *hash, + struct rte_flow_error *error) +{ + struct mlx5_priv *priv = dev->data->dev_private; + struct mlx5dr_crc_encap_entropy_hash_fields data; + enum mlx5dr_crc_encap_entropy_hash_size res_size = + dest_field == RTE_FLOW_ENCAP_HASH_FIELD_SRC_PORT ? + MLX5DR_CRC_ENCAP_ENTROPY_HASH_SIZE_16 : + MLX5DR_CRC_ENCAP_ENTROPY_HASH_SIZE_8; + int res; + + memset(&data, 0, sizeof(struct mlx5dr_crc_encap_entropy_hash_fields)); + + for (; pattern->type != RTE_FLOW_ITEM_TYPE_END; pattern++) { + switch (pattern->type) { + case RTE_FLOW_ITEM_TYPE_IPV4: + data.dst.ipv4_addr = + ((const struct rte_flow_item_ipv4 *)(pattern->spec))->hdr.dst_addr; + data.src.ipv4_addr = + ((const struct rte_flow_item_ipv4 *)(pattern->spec))->hdr.src_addr; + break; + case RTE_FLOW_ITEM_TYPE_IPV6: + memcpy(data.dst.ipv6_addr, + ((const struct rte_flow_item_ipv6 *)(pattern->spec))->hdr.dst_addr, + sizeof(data.dst.ipv6_addr)); + memcpy(data.src.ipv6_addr, + ((const struct rte_flow_item_ipv6 *)(pattern->spec))->hdr.src_addr, + sizeof(data.src.ipv6_addr)); + break; + case RTE_FLOW_ITEM_TYPE_UDP: + data.next_protocol = IPPROTO_UDP; + data.dst_port = + ((const struct rte_flow_item_udp *)(pattern->spec))->hdr.dst_port; + data.src_port = + ((const struct rte_flow_item_udp *)(pattern->spec))->hdr.src_port; + break; + case RTE_FLOW_ITEM_TYPE_TCP: + data.next_protocol = IPPROTO_TCP; + data.dst_port = + ((const struct rte_flow_item_tcp *)(pattern->spec))->hdr.dst_port; + data.src_port = + ((const struct rte_flow_item_tcp *)(pattern->spec))->hdr.src_port; + break; + case RTE_FLOW_ITEM_TYPE_ICMP: + data.next_protocol = IPPROTO_ICMP; + break; + case RTE_FLOW_ITEM_TYPE_ICMP6: + data.next_protocol = IPPROTO_ICMPV6; + break; + default: + break; + } + } + res = mlx5dr_crc_encap_entropy_hash_calc(priv->dr_ctx, &data, hash, res_size); + if (res) + return rte_flow_error_set(error, res, + RTE_FLOW_ERROR_TYPE_UNSPECIFIED, + NULL, "error while calculating encap hash"); + return 0; +} + const struct mlx5_flow_driver_ops mlx5_flow_hw_drv_ops = { .info_get = flow_hw_info_get, .configure = flow_hw_configure, @@ -11746,6 +11811,7 @@ const struct mlx5_flow_driver_ops mlx5_flow_hw_drv_ops = { .item_create = flow_dv_item_create, .item_release = flow_dv_item_release, .flow_calc_table_hash = flow_hw_calc_table_hash, + .flow_calc_encap_hash = flow_hw_calc_encap_hash, }; /**