From patchwork Wed Feb 7 17:13:48 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hernan Vargas X-Patchwork-Id: 136502 X-Patchwork-Delegate: maxime.coquelin@redhat.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id E643143AA1; Wed, 7 Feb 2024 18:17:43 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 2BBAF40295; Wed, 7 Feb 2024 18:17:19 +0100 (CET) Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.18]) by mails.dpdk.org (Postfix) with ESMTP id A5363402BF for ; Wed, 7 Feb 2024 18:17:13 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1707326234; x=1738862234; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=fFr1TLtKWWWeVyZ8bS6esKbyVLECGhU+MrQg/wfeJqs=; b=UT6rRIfEPaYW99tx0Xfyo1Zb1cS+1d6pGAcLLS8ZjDF52MCcrbvens0t BP3xSqCyq+SWXncHblelFmsYjIw6KqgXZmwy+hN2m+txJaJ5Rx/mu53/Q WtCwENxsClim/fnJ85V2OAAtPD+6z1S7bP6aLm+RbeTb/tnNlcLfAb0MO SWlhFFDfaIyA+ZggxCWAr7oBZjHEfYc8IZ95ScPBIloBCTayASrzqKcoe 6NoN2veDTcl2qGFTBStzJjy4D3YBdl1q9bw5TEpACi/T9f+eX0oGbxk+C Jo1MA+YvavgJ1fdBVr4GlWgV6Ix7U2h7hxnG1IlP+mxguVhuUTT/S/M+Z g==; X-IronPort-AV: E=McAfee;i="6600,9927,10977"; a="1185792" X-IronPort-AV: E=Sophos;i="6.05,251,1701158400"; d="scan'208";a="1185792" Received: from fmviesa007.fm.intel.com ([10.60.135.147]) by orvoesa110.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Feb 2024 09:17:12 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.05,251,1701158400"; d="scan'208";a="1410896" Received: from unknown (HELO csl-npg-qt0.la.intel.com) ([10.233.181.103]) by fmviesa007.fm.intel.com with ESMTP; 07 Feb 2024 09:17:11 -0800 From: Hernan Vargas To: dev@dpdk.org, gakhil@marvell.com, trix@redhat.com, maxime.coquelin@redhat.com Cc: nicolas.chautru@intel.com, qi.z.zhang@intel.com, Hernan Vargas Subject: [PATCH v6 4/6] baseband/fpga_5gnr_fec: rework total number queues Date: Wed, 7 Feb 2024 09:13:48 -0800 Message-Id: <20240207171350.242156-5-hernan.vargas@intel.com> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20240207171350.242156-1-hernan.vargas@intel.com> References: <20240207171350.242156-1-hernan.vargas@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Add total_num_queues to the FPGA device struct as a preliminary rework for the introduction of different FPGA variants. Signed-off-by: Hernan Vargas Reviewed-by: Maxime Coquelin --- .../baseband/fpga_5gnr_fec/fpga_5gnr_fec.h | 2 + .../fpga_5gnr_fec/rte_fpga_5gnr_fec.c | 37 +++++++++++-------- 2 files changed, 23 insertions(+), 16 deletions(-) diff --git a/drivers/baseband/fpga_5gnr_fec/fpga_5gnr_fec.h b/drivers/baseband/fpga_5gnr_fec/fpga_5gnr_fec.h index 982e956dc819..879e5467ef3d 100644 --- a/drivers/baseband/fpga_5gnr_fec/fpga_5gnr_fec.h +++ b/drivers/baseband/fpga_5gnr_fec/fpga_5gnr_fec.h @@ -131,6 +131,8 @@ struct fpga_5gnr_fec_device { uint64_t q_assigned_bit_map; /** True if this is a PF FPGA 5GNR device. */ bool pf_device; + /** Maximum number of possible queues for this device. */ + uint8_t total_num_queues; }; /** Structure associated with each queue. */ diff --git a/drivers/baseband/fpga_5gnr_fec/rte_fpga_5gnr_fec.c b/drivers/baseband/fpga_5gnr_fec/rte_fpga_5gnr_fec.c index f9a776e6aea5..3fb505775f61 100644 --- a/drivers/baseband/fpga_5gnr_fec/rte_fpga_5gnr_fec.c +++ b/drivers/baseband/fpga_5gnr_fec/rte_fpga_5gnr_fec.c @@ -203,7 +203,7 @@ fpga_5gnr_setup_queues(struct rte_bbdev *dev, uint16_t num_queues, int socket_id * replaced with a queue ID and if it's not then * FPGA_5GNR_INVALID_HW_QUEUE_ID is returned. */ - for (q_id = 0; q_id < VC_5GNR_TOTAL_NUM_QUEUES; ++q_id) { + for (q_id = 0; q_id < d->total_num_queues; ++q_id) { uint32_t hw_q_id = fpga_5gnr_reg_read_32(d->mmio_base, VC_5GNR_QUEUE_MAP + (q_id << 2)); @@ -367,7 +367,7 @@ fpga_5gnr_dev_info_get(struct rte_bbdev *dev, struct rte_bbdev_driver_info *dev_ /* Calculates number of queues assigned to device */ dev_info->max_num_queues = 0; - for (q_id = 0; q_id < VC_5GNR_TOTAL_NUM_QUEUES; ++q_id) { + for (q_id = 0; q_id < d->total_num_queues; ++q_id) { uint32_t hw_q_id = fpga_5gnr_reg_read_32(d->mmio_base, VC_5GNR_QUEUE_MAP + (q_id << 2)); if (hw_q_id != FPGA_5GNR_INVALID_HW_QUEUE_ID) @@ -394,11 +394,11 @@ fpga_5gnr_find_free_queue_idx(struct rte_bbdev *dev, struct fpga_5gnr_fec_device *d = dev->data->dev_private; uint64_t q_idx; uint8_t i = 0; - uint8_t range = VC_5GNR_TOTAL_NUM_QUEUES >> 1; + uint8_t range = d->total_num_queues >> 1; if (conf->op_type == RTE_BBDEV_OP_LDPC_ENC) { - i = VC_5GNR_NUM_DL_QUEUES; - range = VC_5GNR_TOTAL_NUM_QUEUES; + i = d->total_num_queues >> 1; + range = d->total_num_queues; } for (; i < range; ++i) { @@ -661,7 +661,7 @@ fpga_5gnr_dev_interrupt_handler(void *cb_arg) uint8_t i; /* Scan queue assigned to this device */ - for (i = 0; i < VC_5GNR_TOTAL_NUM_QUEUES; ++i) { + for (i = 0; i < d->total_num_queues; ++i) { q_idx = 1ULL << i; if (d->q_bound_bit_map & q_idx) { queue_id = get_queue_id(dev->data, i); @@ -710,22 +710,25 @@ fpga_5gnr_intr_enable(struct rte_bbdev *dev) { int ret; uint8_t i; + struct fpga_5gnr_fec_device *d = dev->data->dev_private; + uint8_t num_intr_vec; + num_intr_vec = d->total_num_queues - RTE_INTR_VEC_RXTX_OFFSET; if (!rte_intr_cap_multiple(dev->intr_handle)) { rte_bbdev_log(ERR, "Multiple intr vector is not supported by FPGA (%s)", dev->data->name); return -ENOTSUP; } - /* Create event file descriptors for each of 64 queue. Event fds will be - * mapped to FPGA IRQs in rte_intr_enable(). This is a 1:1 mapping where - * the IRQ number is a direct translation to the queue number. + /* Create event file descriptors for each of the supported queues (Maximum 64). + * Event fds will be mapped to FPGA IRQs in rte_intr_enable(). + * This is a 1:1 mapping where the IRQ number is a direct translation to the queue number. * - * 63 (VC_5GNR_NUM_INTR_VEC) event fds are created as rte_intr_enable() + * num_intr_vec event fds are created as rte_intr_enable() * mapped the first IRQ to already created interrupt event file * descriptor (intr_handle->fd). */ - if (rte_intr_efd_enable(dev->intr_handle, VC_5GNR_NUM_INTR_VEC)) { + if (rte_intr_efd_enable(dev->intr_handle, num_intr_vec)) { rte_bbdev_log(ERR, "Failed to create fds for %u queues", dev->data->num_queues); return -1; } @@ -735,7 +738,7 @@ fpga_5gnr_intr_enable(struct rte_bbdev *dev) * It ensures that callback function assigned to that descriptor will * invoked when any FPGA queue issues interrupt. */ - for (i = 0; i < VC_5GNR_NUM_INTR_VEC; ++i) { + for (i = 0; i < num_intr_vec; ++i) { if (rte_intr_efds_index_set(dev->intr_handle, i, rte_intr_fd_get(dev->intr_handle))) return -rte_errno; @@ -2083,6 +2086,8 @@ fpga_5gnr_fec_init(struct rte_bbdev *dev, struct rte_pci_driver *drv) !strcmp(drv->driver.name, RTE_STR(FPGA_5GNR_FEC_PF_DRIVER_NAME)); ((struct fpga_5gnr_fec_device *) dev->data->dev_private)->mmio_base = pci_dev->mem_resource[0].addr; + ((struct fpga_5gnr_fec_device *) dev->data->dev_private)->total_num_queues = + VC_5GNR_TOTAL_NUM_QUEUES; rte_bbdev_log_debug( "Init device %s [%s] @ virtaddr %p phyaddr %#"PRIx64, @@ -2242,7 +2247,7 @@ static int vc_5gnr_configure(const char *dev_name, const struct rte_fpga_5gnr_fe /* Clear all queues registers */ payload_32 = FPGA_5GNR_INVALID_HW_QUEUE_ID; - for (q_id = 0; q_id < VC_5GNR_TOTAL_NUM_QUEUES; ++q_id) { + for (q_id = 0; q_id < d->total_num_queues; ++q_id) { address = (q_id << 2) + VC_5GNR_QUEUE_MAP; fpga_5gnr_reg_write_32(d->mmio_base, address, payload_32); } @@ -2303,7 +2308,7 @@ static int vc_5gnr_configure(const char *dev_name, const struct rte_fpga_5gnr_fe */ if (conf->pf_mode_en) { payload_32 = 0x1; - for (q_id = 0; q_id < VC_5GNR_TOTAL_NUM_QUEUES; ++q_id) { + for (q_id = 0; q_id < d->total_num_queues; ++q_id) { address = (q_id << 2) + VC_5GNR_QUEUE_MAP; fpga_5gnr_reg_write_32(d->mmio_base, address, payload_32); } @@ -2321,11 +2326,11 @@ static int vc_5gnr_configure(const char *dev_name, const struct rte_fpga_5gnr_fe */ if ((total_ul_q_id > VC_5GNR_NUM_UL_QUEUES) || (total_dl_q_id > VC_5GNR_NUM_DL_QUEUES) || - (total_q_id > VC_5GNR_TOTAL_NUM_QUEUES)) { + (total_q_id > d->total_num_queues)) { rte_bbdev_log(ERR, "VC 5GNR FPGA Configuration failed. Too many queues to configure: UL_Q %u, DL_Q %u, FPGA_Q %u", total_ul_q_id, total_dl_q_id, - VC_5GNR_TOTAL_NUM_QUEUES); + d->total_num_queues); return -EINVAL; } total_ul_q_id = 0;