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Wed, 7 Feb 2024 08:20:48 -0800 From: Michael Baum To: CC: Matan Azrad , Dariusz Sosnowski , Raslan Darawsheh , Viacheslav Ovsiienko , Ori Kam , Suanming Mou Subject: [PATCH] net/mlx5/hws: add compare ESP sequence number support Date: Wed, 7 Feb 2024 18:20:23 +0200 Message-ID: <20240207162023.1583557-1-michaelba@nvidia.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH1PEPF0000A34B:EE_|SJ0PR12MB7005:EE_ X-MS-Office365-Filtering-Correlation-Id: e5608c32-98dc-48d0-2383-08dc27f8c843 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: Tah7xffHYifoGt8xGUR/JrEqtQWAz023Vw2N7cxcixfeuwHRBOvb3P3mraY7l6YEgSNOXeeo4gFQmFXaakiyWPX+jab9EERPtx4ZrmbgR5E/XNXPPxU0TRzMuCwZyHzfgVg0Npp5Vl70M0B7yqWHxbs4eDPoFtoUdp/mMLUklmoFKxV3ZNlVgktYqt7BHklCfBPbv1n0MxfqZ//y7TwqO/4arrQ/j/SQoZWVhAWy68BHPXi76ke5fQVeqO0KjLjtEXsK+/oD9DiCHMUQTqRNiHXZgGyzOzCp+wepADg6CQu+JgvAmoo0G2bhK5KDn7QJrq6WfmqBZMxy8uGhvYZ2dbeZ6k+vrBBm7nOwvfPSDR2i3acFN0qttnjOCKORFCmdWn4M0rwfpg3nZRFm4gUaxHbYFhHJZyr8I2hSQcj64LEEMs3hpxI5yJ96julgIO1WCK9p69dge8qMefmdqwD7pGrsRAJFBI85w6w3eQJ/YJb6jPVbNWtM4kJwSNZYONfyDs2LlYX42lluvaohCaOJsq7FJb3vKbhtbKto26laz1I8QLjCMotmO1DpFWlhu7Y6Nxkf3F8XDGF181sUQn3WDO69HMUNKXe/i1SDIaoaUNMTtflywqzMQUUsViwRn4kgT5T/1bVRjXa1lHGgYxU/AMxGAS/OsOPmN7fmnxiZSeFr1bRTs6rExPFktSLLObM1wN4Xy2Ce/wRdf9iHqVujlhnnb7J6aSj3dMy6RX+zLua1iD/exjGur64man73WAUs X-Forefront-Antispam-Report: CIP:216.228.118.232; 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Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CH1PEPF0000A34B.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ0PR12MB7005 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Add support for compare item with "RTE_FLOW_FIELD_ESP_SEQ_NUM" field. Signed-off-by: Michael Baum --- Depends-on: series-31008 ("ethdev: add modify IPv4 next protocol field") Depends-on: series-31041 ("net/mlx5: add random compare support") doc/guides/nics/mlx5.rst | 1 + drivers/net/mlx5/hws/mlx5dr_definer.c | 22 ++++++++++++++++++++-- drivers/net/mlx5/mlx5_flow_hw.c | 3 +++ 3 files changed, 24 insertions(+), 2 deletions(-) diff --git a/doc/guides/nics/mlx5.rst b/doc/guides/nics/mlx5.rst index 43ef8a99dc..b793f1ef58 100644 --- a/doc/guides/nics/mlx5.rst +++ b/doc/guides/nics/mlx5.rst @@ -823,6 +823,7 @@ Limitations - Only single item is supported per pattern template. - Only 32-bit comparison is supported or 16-bits for random field. - Only supported for ``RTE_FLOW_FIELD_META``, ``RTE_FLOW_FIELD_TAG``, + ``RTE_FLOW_FIELD_ESP_SEQ_NUM``, ``RTE_FLOW_FIELD_RANDOM`` and ``RTE_FLOW_FIELD_VALUE``. - The field type ``RTE_FLOW_FIELD_VALUE`` must be the base (``b``) field. - The field type ``RTE_FLOW_FIELD_RANDOM`` can only be compared with diff --git a/drivers/net/mlx5/hws/mlx5dr_definer.c b/drivers/net/mlx5/hws/mlx5dr_definer.c index 2d86175ca2..b29d7451e7 100644 --- a/drivers/net/mlx5/hws/mlx5dr_definer.c +++ b/drivers/net/mlx5/hws/mlx5dr_definer.c @@ -396,10 +396,20 @@ mlx5dr_definer_compare_base_value_set(const void *item_spec, value = (const uint32_t *)&b->value[0]; - if (a->field == RTE_FLOW_FIELD_RANDOM) + switch (a->field) { + case RTE_FLOW_FIELD_RANDOM: *base = htobe32(*value << 16); - else + break; + case RTE_FLOW_FIELD_TAG: + case RTE_FLOW_FIELD_META: *base = htobe32(*value); + break; + case RTE_FLOW_FIELD_ESP_SEQ_NUM: + *base = *value; + break; + default: + break; + } MLX5_SET(ste_match_4dw_range_ctrl_dw, ctrl, base0, 1); } @@ -2887,6 +2897,14 @@ mlx5dr_definer_conv_item_compare_field(const struct rte_flow_field_data *f, fc->compare_idx = dw_offset; DR_CALC_SET_HDR(fc, random_number, random_number); break; + case RTE_FLOW_FIELD_ESP_SEQ_NUM: + fc = &cd->fc[MLX5DR_DEFINER_FNAME_ESP_SEQUENCE_NUMBER]; + fc->item_idx = item_idx; + fc->tag_set = &mlx5dr_definer_compare_set; + fc->tag_mask_set = &mlx5dr_definer_ones_set; + fc->compare_idx = dw_offset; + DR_CALC_SET_HDR(fc, ipsec, sequence_number); + break; default: DR_LOG(ERR, "%u field is not supported", f->field); goto err_notsup; diff --git a/drivers/net/mlx5/mlx5_flow_hw.c b/drivers/net/mlx5/mlx5_flow_hw.c index b5741f0817..4d6fb489b2 100644 --- a/drivers/net/mlx5/mlx5_flow_hw.c +++ b/drivers/net/mlx5/mlx5_flow_hw.c @@ -6725,6 +6725,7 @@ flow_hw_item_compare_field_validate(enum rte_flow_field_id arg_field, switch (arg_field) { case RTE_FLOW_FIELD_TAG: case RTE_FLOW_FIELD_META: + case RTE_FLOW_FIELD_ESP_SEQ_NUM: break; case RTE_FLOW_FIELD_RANDOM: if (base_field == RTE_FLOW_FIELD_VALUE) @@ -6743,6 +6744,7 @@ flow_hw_item_compare_field_validate(enum rte_flow_field_id arg_field, case RTE_FLOW_FIELD_TAG: case RTE_FLOW_FIELD_META: case RTE_FLOW_FIELD_VALUE: + case RTE_FLOW_FIELD_ESP_SEQ_NUM: break; default: return rte_flow_error_set(error, ENOTSUP, @@ -6759,6 +6761,7 @@ flow_hw_item_compare_width_supported(enum rte_flow_field_id field) switch (field) { case RTE_FLOW_FIELD_TAG: case RTE_FLOW_FIELD_META: + case RTE_FLOW_FIELD_ESP_SEQ_NUM: return 32; case RTE_FLOW_FIELD_RANDOM: return 16;