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DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 07 Feb 2024 12:29:52.8212 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e91a465f-f8ec-4e4f-a601-08dc27d87c2e X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000EDD6.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR12MB7125 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Add mlx5 PMD support for the IPsec fields: - RTE_FLOW_FIELD_ESP_SPI - SPI value in IPsec header - RTE_FLOW_FIELD_ESP_SEQ_NUM - sequence number in header - RTE_FLOW_FIELD_ESP_PROTO - next protocol value in trailer Signed-off-by: Viacheslav Ovsiienko Acked-by: Dariusz Sosnowski --- doc/guides/rel_notes/release_24_03.rst | 3 +++ drivers/common/mlx5/mlx5_prm.h | 3 +++ drivers/net/mlx5/mlx5_flow_dv.c | 31 ++++++++++++++++++++++++++ 3 files changed, 37 insertions(+) diff --git a/doc/guides/rel_notes/release_24_03.rst b/doc/guides/rel_notes/release_24_03.rst index d0c3389287..0f8d2fd81c 100644 --- a/doc/guides/rel_notes/release_24_03.rst +++ b/doc/guides/rel_notes/release_24_03.rst @@ -112,6 +112,9 @@ New Features * Added HW steering support for modify field ``RTE_FLOW_FIELD_GENEVE_OPT_CLASS`` flow action. * Added HW steering support for modify field ``RTE_FLOW_FIELD_GENEVE_OPT_DATA`` flow action. * Added HW steering support for modify field ``RTE_FLOW_FIELD_IPV4_PROTO`` flow action. + * Added HW steering support for modify field ``RTE_FLOW_FIELD_ESP_SPI`` flow action. + * Added HW steering support for modify field ``RTE_FLOW_FIELD_ESP_SEQ_NUM`` flow action. + * Added HW steering support for modify field ``RTE_FLOW_FIELD_ESP_PROTO`` flow action. Removed Items diff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h index 3168ce76a5..0035a1e616 100644 --- a/drivers/common/mlx5/mlx5_prm.h +++ b/drivers/common/mlx5/mlx5_prm.h @@ -854,6 +854,9 @@ enum mlx5_modification_field { MLX5_MODI_OUT_IPV6_PAYLOAD_LEN = 0x11E, MLX5_MODI_OUT_IPV4_IHL = 0x11F, MLX5_MODI_OUT_TCP_DATA_OFFSET = 0x120, + MLX5_MODI_OUT_ESP_SPI = 0x5E, + MLX5_MODI_OUT_ESP_SEQ_NUM = 0x82, + MLX5_MODI_OUT_IPSEC_NEXT_HDR = 0x126, MLX5_MODI_INVALID = INT_MAX, }; diff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c index eb7cbf808c..6fded15d91 100644 --- a/drivers/net/mlx5/mlx5_flow_dv.c +++ b/drivers/net/mlx5/mlx5_flow_dv.c @@ -1414,7 +1414,11 @@ mlx5_flow_item_field_width(struct rte_eth_dev *dev, case RTE_FLOW_FIELD_GTP_TEID: case RTE_FLOW_FIELD_MPLS: case RTE_FLOW_FIELD_TAG: + case RTE_FLOW_FIELD_ESP_SPI: + case RTE_FLOW_FIELD_ESP_SEQ_NUM: return 32; + case RTE_FLOW_FIELD_ESP_PROTO: + return 8; case RTE_FLOW_FIELD_MARK: return rte_popcount32(priv->sh->dv_mark_mask); case RTE_FLOW_FIELD_META: @@ -2205,6 +2209,33 @@ mlx5_flow_field_id_to_modify_info else info[idx].offset = off_be; break; + case RTE_FLOW_FIELD_ESP_PROTO: + MLX5_ASSERT(data->offset + width <= 8); + off_be = 8 - (data->offset + width); + info[idx] = (struct field_modify_info){1, 0, MLX5_MODI_OUT_IPSEC_NEXT_HDR}; + if (mask) + mask[idx] = flow_modify_info_mask_8(width, off_be); + else + info[idx].offset = off_be; + break; + case RTE_FLOW_FIELD_ESP_SPI: + MLX5_ASSERT(data->offset + width <= 32); + off_be = 32 - (data->offset + width); + info[idx] = (struct field_modify_info){4, 0, MLX5_MODI_OUT_ESP_SPI}; + if (mask) + mask[idx] = flow_modify_info_mask_32(width, off_be); + else + info[idx].offset = off_be; + break; + case RTE_FLOW_FIELD_ESP_SEQ_NUM: + MLX5_ASSERT(data->offset + width <= 32); + off_be = 32 - (data->offset + width); + info[idx] = (struct field_modify_info){4, 0, MLX5_MODI_OUT_ESP_SEQ_NUM}; + if (mask) + mask[idx] = flow_modify_info_mask_32(width, off_be); + else + info[idx].offset = off_be; + break; case RTE_FLOW_FIELD_FLEX_ITEM: MLX5_ASSERT(data->flex_handle != NULL && !(data->offset & 0x7)); mlx5_modify_flex_item(dev, (const struct mlx5_flex_item *)data->flex_handle,