From patchwork Wed Feb 7 12:13:54 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Slava Ovsiienko X-Patchwork-Id: 136476 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id E12F343A46; Wed, 7 Feb 2024 13:14:48 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id B3BEC42DE9; Wed, 7 Feb 2024 13:14:46 +0100 (CET) Received: from NAM11-DM6-obe.outbound.protection.outlook.com (mail-dm6nam11on2068.outbound.protection.outlook.com [40.107.223.68]) by mails.dpdk.org (Postfix) with ESMTP id 4CA2442DE9 for ; Wed, 7 Feb 2024 13:14:45 +0100 (CET) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=JJpvmoZbu4KTdhPes3WK8gqfKcvKPRisCA6FMqxkYbBW9Boptm6XXkjsbIZNyp6p/zTcKapetPW/ydEfimpuQryQc6KjGpK60hVf630zitJ/+HkL0uNMqSLYk/N+KViEqsC7PIa/dJTsHiDlUTcPTK0U+TBKEqH+RBUjgSPJ342GU/08UFYsoLNtDaKX498fnywXcgb27w5iuBJbVG6w9CWTAie9QXLCEuBfc9EGT1i2K6RfXHNAs4ObHnjwmK513CQB01O2q1LkRi8JKTDAmwE0+NhXM0cdBZZcLH2XeOJBFvzqqs8APUPEdE73Pk7A0ZwzyOxurtNd/Z1UpxgYrw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=/YALnA6Vmw5v2XfvhxIcFXZvfRAaRefgISnjdKy0yIY=; b=TbkI87Fscmz2EieoAB7C5wRk9+HohGEfAA1CvmTDKQ48h82N7nw1WoWgyHVWhzF/xOSX6JQk8TnS4NSJps7XsnJcFiz5M4SWb7gi5YwDvu6cnRFLo3+/irTmgp17PwCq0pn/sJY1XtoYSNZiqqpPVIPvr7AHUBacerxA/YoZx/xLCOJGSmtAklB8cYsuY9zRGDaPON+NEM2vOkxFLBYMbujCLssp4CHRUoq4fRV2xy6Kr6BhUHrwZm4RupW28dyJVpNnShQ0K8ai0xPYqEFTD4TbBvVW32uceQaNM7WprqRvY4T73nSrzHkJqw7GbU4t9bK2PEGb0M72HyxXJgkKaw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.161) smtp.rcpttodomain=dpdk.org smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=/YALnA6Vmw5v2XfvhxIcFXZvfRAaRefgISnjdKy0yIY=; b=S0pCOmTDTfpJRkYeSVb/3YC4u8IbjxiA/0ItUKfyDfUzXdH/ayOsdNQx6w67MTX48ejL4Ck9HIEyU1uvYtR17z2zxuEUqW61tshY2oJTHArwp+BquJl6eOlGczx9LfyGsv4xU3csdbcIcTLK5Kd8VVvbKUbRXMvMJjktIKuUGuL6Zb4OHHpLfEUeqMC7Qme6PRWnYMXqxElxt6jZdPSR//T5IRz5R2dBTXp48ebRlD7E1gQ+S0IyfvC0kkzx7fYOYUk6v9ClV5v5BL5SSFT610B5oQdyVG3K9lr8NiZGf/wFgCxeRhb7hdVhipwSsITsCNifGNsPN8iCiI2EpGQ9ZQ== Received: from BN9PR03CA0295.namprd03.prod.outlook.com (2603:10b6:408:f5::30) by SN7PR12MB7346.namprd12.prod.outlook.com (2603:10b6:806:299::16) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7270.16; Wed, 7 Feb 2024 12:14:42 +0000 Received: from BN3PEPF0000B06C.namprd21.prod.outlook.com (2603:10b6:408:f5:cafe::e7) by BN9PR03CA0295.outlook.office365.com (2603:10b6:408:f5::30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7249.36 via Frontend Transport; Wed, 7 Feb 2024 12:14:42 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.161) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.161 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.161; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.161) by BN3PEPF0000B06C.mail.protection.outlook.com (10.167.243.71) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7292.0 via Frontend Transport; Wed, 7 Feb 2024 12:14:42 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.67) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.41; Wed, 7 Feb 2024 04:14:24 -0800 Received: from nvidia.com (10.126.231.35) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.12; Wed, 7 Feb 2024 04:14:22 -0800 From: Viacheslav Ovsiienko To: CC: , , , Subject: [PATCH v2 6/6] net/mlx5: add modify field action IPsec support Date: Wed, 7 Feb 2024 14:13:54 +0200 Message-ID: <20240207121354.27175-6-viacheslavo@nvidia.com> X-Mailer: git-send-email 2.18.1 In-Reply-To: <20240207121354.27175-1-viacheslavo@nvidia.com> References: <20240207121354.27175-1-viacheslavo@nvidia.com> MIME-Version: 1.0 X-Originating-IP: [10.126.231.35] X-ClientProxiedBy: rnnvmail203.nvidia.com (10.129.68.9) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN3PEPF0000B06C:EE_|SN7PR12MB7346:EE_ X-MS-Office365-Filtering-Correlation-Id: a9405502-f437-4d30-4dfe-08dc27d65da8 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: SnJEKviV0pQMZx1R/xWRUeLqCt/0PsgWOraffhoU3zSOxcUgXmdzG2qq5mO1Pj0gv+0eaZqTIyqEy2Djko7BLQcFx67D+oewUfKzoZ5+/HWYCFCndb8uI6YI0FHSsRTuNLX4QyBh3FbiyG4r8sXwNmEb+o1VnyKpWFwglPEgN9yKHhOVH3JDsZp9dpQoeWQ1jgcQNJy0KkM0vsHkGXyTGhh8N69/FOGBv+gRf/WLa8fa84n1VTeRLYEs8L1X7fLkeUT2PX56BcwRdWe4XQW+l99N2V8zBSAadBvIVdsYZr20/1w9cl6xsLFKeyAG4IWZZtbs2cJZLsePZ+MciogowEM/6Ivq5LZ0KCRt7QiHgCVx4lWViad7jdczPI9+VHN7BhxtAnnmmW+vAgtlI2SpWb1bxKGW4lvLGZXLu3D1O6bKW5PE0mTbatEmBMDdzT8c/bMpbwLBYzkrsoK2SfyDY+qlALsGiTbse1pJtKj6l6dlXEer6hg92tacCtdRKTtJzP5J/x9stt+26jRRT5n6kJ0wjGB0N1YI7eOPe8txGnu7dyc7u0UpyRWZdkamMwabrrtXWghDhS5pONy1mTDyme2XciRg2CPpOs6w1ow8yUIczgt/IGpuoYhJY9kKYE6dQ8slbHHLVrl7yF3wFztJgxLSo44/UdxUYvdSMeTX9RdDDYuQg5TkwjmbMgHKfTFbN212fzA4+7j0xz9P0CrLLVOSuWGNELwD6IYYDVwYFsSLT7LJyFaxdGUTteJJTuVC X-Forefront-Antispam-Report: CIP:216.228.117.161; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge2.nvidia.com; CAT:NONE; SFS:(13230031)(4636009)(346002)(136003)(39860400002)(376002)(396003)(230922051799003)(186009)(64100799003)(451199024)(82310400011)(1800799012)(46966006)(40470700004)(36840700001)(6286002)(5660300002)(7636003)(41300700001)(55016003)(82740400003)(2906002)(6916009)(47076005)(54906003)(356005)(107886003)(8676002)(40480700001)(4326008)(8936002)(426003)(336012)(40460700003)(16526019)(26005)(70586007)(1076003)(316002)(2616005)(86362001)(70206006)(36860700001)(36756003)(7696005)(478600001)(6666004); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 07 Feb 2024 12:14:42.5532 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a9405502-f437-4d30-4dfe-08dc27d65da8 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN3PEPF0000B06C.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN7PR12MB7346 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Add mlx5 PMD support for the IPsec fields: - RTE_FLOW_FIELD_ESP_SPI - SPI value in IPsec header - RTE_FLOW_FIELD_ESP_SEQ_NUM - sequence number in header - RTE_FLOW_FIELD_ESP_PROTO - next protocol value in trailer Signed-off-by: Viacheslav Ovsiienko Acked-by: Dariusz Sosnowski --- doc/guides/rel_notes/release_24_03.rst | 3 +++ drivers/common/mlx5/mlx5_prm.h | 3 +++ drivers/net/mlx5/mlx5_flow_dv.c | 31 ++++++++++++++++++++++++++ 3 files changed, 37 insertions(+) diff --git a/doc/guides/rel_notes/release_24_03.rst b/doc/guides/rel_notes/release_24_03.rst index 0403157202..189724f660 100644 --- a/doc/guides/rel_notes/release_24_03.rst +++ b/doc/guides/rel_notes/release_24_03.rst @@ -98,6 +98,9 @@ New Features * Added HW steering support for modify field ``RTE_FLOW_FIELD_GENEVE_OPT_CLASS`` flow action. * Added HW steering support for modify field ``RTE_FLOW_FIELD_GENEVE_OPT_DATA`` flow action. * Added HW steering support for modify field ``RTE_FLOW_FIELD_IPV4_PROTO`` flow action. + * Added HW steering support for modify field ``RTE_FLOW_FIELD_ESP_SPI`` flow action. + * Added HW steering support for modify field ``RTE_FLOW_FIELD_ESP_SEQ_NUM`` flow action. + * Added HW steering support for modify field ``RTE_FLOW_FIELD_ESP_PROTO`` flow action. Removed Items diff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h index 44413517d0..3150412580 100644 --- a/drivers/common/mlx5/mlx5_prm.h +++ b/drivers/common/mlx5/mlx5_prm.h @@ -854,6 +854,9 @@ enum mlx5_modification_field { MLX5_MODI_OUT_IPV6_PAYLOAD_LEN = 0x11E, MLX5_MODI_OUT_IPV4_IHL = 0x11F, MLX5_MODI_OUT_TCP_DATA_OFFSET = 0x120, + MLX5_MODI_OUT_ESP_SPI = 0x5E, + MLX5_MODI_OUT_ESP_SEQ_NUM = 0x82, + MLX5_MODI_OUT_IPSEC_NEXT_HDR = 0x126, MLX5_MODI_INVALID = INT_MAX, }; diff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c index 764940b700..90413f4a38 100644 --- a/drivers/net/mlx5/mlx5_flow_dv.c +++ b/drivers/net/mlx5/mlx5_flow_dv.c @@ -1414,7 +1414,11 @@ mlx5_flow_item_field_width(struct rte_eth_dev *dev, case RTE_FLOW_FIELD_GTP_TEID: case RTE_FLOW_FIELD_MPLS: case RTE_FLOW_FIELD_TAG: + case RTE_FLOW_FIELD_ESP_SPI: + case RTE_FLOW_FIELD_ESP_SEQ_NUM: return 32; + case RTE_FLOW_FIELD_ESP_PROTO: + return 8; case RTE_FLOW_FIELD_MARK: return rte_popcount32(priv->sh->dv_mark_mask); case RTE_FLOW_FIELD_META: @@ -2205,6 +2209,33 @@ mlx5_flow_field_id_to_modify_info else info[idx].offset = off_be; break; + case RTE_FLOW_FIELD_ESP_PROTO: + MLX5_ASSERT(data->offset + width <= 8); + off_be = 8 - (data->offset + width); + info[idx] = (struct field_modify_info){1, 0, MLX5_MODI_OUT_IPSEC_NEXT_HDR}; + if (mask) + mask[idx] = flow_modify_info_mask_8(width, off_be); + else + info[idx].offset = off_be; + break; + case RTE_FLOW_FIELD_ESP_SPI: + MLX5_ASSERT(data->offset + width <= 32); + off_be = 32 - (data->offset + width); + info[idx] = (struct field_modify_info){4, 0, MLX5_MODI_OUT_ESP_SPI}; + if (mask) + mask[idx] = flow_modify_info_mask_32(width, off_be); + else + info[idx].offset = off_be; + break; + case RTE_FLOW_FIELD_ESP_SEQ_NUM: + MLX5_ASSERT(data->offset + width <= 32); + off_be = 32 - (data->offset + width); + info[idx] = (struct field_modify_info){4, 0, MLX5_MODI_OUT_ESP_SEQ_NUM}; + if (mask) + mask[idx] = flow_modify_info_mask_32(width, off_be); + else + info[idx].offset = off_be; + break; case RTE_FLOW_FIELD_FLEX_ITEM: MLX5_ASSERT(data->flex_handle != NULL && !(data->offset & 0x7)); mlx5_modify_flex_item(dev, (const struct mlx5_flex_item *)data->flex_handle,