From patchwork Sun Jan 7 15:40:10 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Srikanth Yalavarthi X-Patchwork-Id: 135789 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 9B03643857; Sun, 7 Jan 2024 16:40:37 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 4DDFA406BC; Sun, 7 Jan 2024 16:40:29 +0100 (CET) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id A86D74027E for ; Sun, 7 Jan 2024 16:40:26 +0100 (CET) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.17.1.24/8.17.1.24) with ESMTP id 407EUkE8010955 for ; Sun, 7 Jan 2024 07:40:26 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:content-type; s= pfpt0220; bh=mQkr+rLnJAKoBx2qLnMsV2MXdTmmQbzGjC4HWqmPACI=; b=VI7 j1R2ZWR3f0407SJt8fyhC4Aa+3wOeursNSD6+8fDGNqEkTXj39igQMka3PhuZEz5 +8F//slzG7f/pFbhhVsJENCHDIunEtl+EeFSe4urnmOJszSlz4qDFXbu2hV/QkEB 4iZ+WnqSPsfPCRDrqLAgtHMZptWrutcG/FzZj7mJXzEmaPq4AjDDUJXTzVQdL56a kUaqmty/7oRM3ls43TpcdQbspyYnyeRFzmAtT2K9G/sIYUObvIXduuNkR/YH4vAg 9hNxiSbePFidWgncOYLszLxrAkNS2E0bs/LzHo6MItBjH3oh+ivL/YELy3cWnVZc 9iJLGIJxiXa+i3okL1A== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3vf78n2ac9-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Sun, 07 Jan 2024 07:40:25 -0800 (PST) Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.48; Sun, 7 Jan 2024 07:40:23 -0800 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.48 via Frontend Transport; Sun, 7 Jan 2024 07:40:23 -0800 Received: from ml-host-33.caveonetworks.com (unknown [10.110.143.233]) by maili.marvell.com (Postfix) with ESMTP id 3241D3F709E; Sun, 7 Jan 2024 07:40:23 -0800 (PST) From: Srikanth Yalavarthi To: Pavan Nikhilesh , Shijith Thotton , Srikanth Yalavarthi CC: , , , , Subject: [PATCH 1/4] event/cnxk: add ML adapter capabilities get Date: Sun, 7 Jan 2024 07:40:10 -0800 Message-ID: <20240107154013.4676-2-syalavarthi@marvell.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20240107154013.4676-1-syalavarthi@marvell.com> References: <20240107154013.4676-1-syalavarthi@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: QWSh0CdIT6W0uzNv8NSW6MB9TaYEVR0z X-Proofpoint-GUID: QWSh0CdIT6W0uzNv8NSW6MB9TaYEVR0z X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.997,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-12-09_02,2023-12-07_01,2023-05-22_02 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Implemented driver function to get ML adapter capabilities. Signed-off-by: Srikanth Yalavarthi --- Depends-on: series-30752 ("Introduce Event ML Adapter") drivers/event/cnxk/cn10k_eventdev.c | 15 +++++++++++++++ drivers/event/cnxk/meson.build | 2 +- drivers/ml/cnxk/cn10k_ml_ops.h | 2 ++ 3 files changed, 18 insertions(+), 1 deletion(-) diff --git a/drivers/event/cnxk/cn10k_eventdev.c b/drivers/event/cnxk/cn10k_eventdev.c index bb0c9105535..09eff569052 100644 --- a/drivers/event/cnxk/cn10k_eventdev.c +++ b/drivers/event/cnxk/cn10k_eventdev.c @@ -6,6 +6,7 @@ #include "cn10k_worker.h" #include "cn10k_ethdev.h" #include "cn10k_cryptodev_ops.h" +#include "cnxk_ml_ops.h" #include "cnxk_eventdev.h" #include "cnxk_worker.h" @@ -1020,6 +1021,18 @@ cn10k_crypto_adapter_vec_limits(const struct rte_eventdev *event_dev, return 0; } +static int +cn10k_ml_adapter_caps_get(const struct rte_eventdev *event_dev, const struct rte_ml_dev *mldev, + uint32_t *caps) +{ + CNXK_VALID_DEV_OR_ERR_RET(event_dev->dev, "event_cn10k", EINVAL); + CNXK_VALID_DEV_OR_ERR_RET(mldev->device, "ml_cn10k", EINVAL); + + *caps = RTE_EVENT_ML_ADAPTER_CAP_INTERNAL_PORT_OP_FWD; + + return 0; +} + static struct eventdev_ops cn10k_sso_dev_ops = { .dev_infos_get = cn10k_sso_info_get, .dev_configure = cn10k_sso_dev_configure, @@ -1061,6 +1074,8 @@ static struct eventdev_ops cn10k_sso_dev_ops = { .crypto_adapter_queue_pair_del = cn10k_crypto_adapter_qp_del, .crypto_adapter_vector_limits_get = cn10k_crypto_adapter_vec_limits, + .ml_adapter_caps_get = cn10k_ml_adapter_caps_get, + .xstats_get = cnxk_sso_xstats_get, .xstats_reset = cnxk_sso_xstats_reset, .xstats_get_names = cnxk_sso_xstats_get_names, diff --git a/drivers/event/cnxk/meson.build b/drivers/event/cnxk/meson.build index 13281d687f7..e09ad97b660 100644 --- a/drivers/event/cnxk/meson.build +++ b/drivers/event/cnxk/meson.build @@ -316,7 +316,7 @@ foreach flag: extra_flags endforeach headers = files('rte_pmd_cnxk_eventdev.h') -deps += ['bus_pci', 'common_cnxk', 'net_cnxk', 'crypto_cnxk'] +deps += ['bus_pci', 'common_cnxk', 'net_cnxk', 'crypto_cnxk', 'ml_cnxk'] require_iova_in_mbuf = false diff --git a/drivers/ml/cnxk/cn10k_ml_ops.h b/drivers/ml/cnxk/cn10k_ml_ops.h index eb3e1c139c7..d225ed2098e 100644 --- a/drivers/ml/cnxk/cn10k_ml_ops.h +++ b/drivers/ml/cnxk/cn10k_ml_ops.h @@ -10,6 +10,8 @@ #include +#include "cnxk_ml_xstats.h" + struct cnxk_ml_dev; struct cnxk_ml_qp; struct cnxk_ml_model;