From patchwork Tue Dec 19 15:51:20 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ciara Power X-Patchwork-Id: 135337 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 0F22043746; Tue, 19 Dec 2023 16:51:41 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 1FB7E42E1A; Tue, 19 Dec 2023 16:51:36 +0100 (CET) Received: from mgamail.intel.com (mgamail.intel.com [134.134.136.65]) by mails.dpdk.org (Postfix) with ESMTP id 780A8402E0 for ; Tue, 19 Dec 2023 16:51:34 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1703001094; x=1734537094; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=I5kH724hj13PjqtFe5eY072R8DpUa+xuC+eW0PD/mmM=; b=K2o+38GOU4AbT3GiWU80iBTiA/4Ai8ZP9eBpnrZhQ0iicIHSezg9npzp f1r9YaFHmvc/XbGkF+DTFFJBz7tUxQv7sOfc6hAwZyS3X5PZ0hFbxhs4Z i8kG8J/csD1DNaOCB4qkur2UmFY+8e/zYLEu0V1Sqz/vLJIP0uc4aMvty kiZyhoWDS6CvkmSZUF/qv8nmlpeHEZbm9nd4J25kyBXRiWH86gCLvcjep 1DI6rYSvdlwnoHS/vkn5o+2QR06unXJznCdOahKVgIZa1a0ZCoNzfz2Rs MQE2dTAyglCOogonUVlXsapkycWPAWJQmk4N7Ela2+S/w8wtig0fsINLl A==; X-IronPort-AV: E=McAfee;i="6600,9927,10929"; a="399510246" X-IronPort-AV: E=Sophos;i="6.04,288,1695711600"; d="scan'208";a="399510246" Received: from orsmga002.jf.intel.com ([10.7.209.21]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Dec 2023 07:51:34 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10929"; a="776021687" X-IronPort-AV: E=Sophos;i="6.04,288,1695711600"; d="scan'208";a="776021687" Received: from silpixa00400355.ir.intel.com (HELO silpixa00400355.ger.corp.intel.com) ([10.237.222.80]) by orsmga002.jf.intel.com with ESMTP; 19 Dec 2023 07:51:32 -0800 From: Ciara Power To: dev@dpdk.org Cc: Ciara Power , Kai Ji Subject: [PATCH 1/4] crypto/qat: add new gen3 device Date: Tue, 19 Dec 2023 15:51:20 +0000 Message-Id: <20231219155124.4133385-2-ciara.power@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20231219155124.4133385-1-ciara.power@intel.com> References: <20231219155124.4133385-1-ciara.power@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Add new gen3 QAT device ID. This device has a wireless slice, but other gen3 devices do not, so we must set a flag to indicate this wireless enabled device. Capabilities for the device are slightly different from base gen3 capabilities, some are removed from the list for this device. Signed-off-by: Ciara Power --- drivers/common/qat/qat_device.c | 13 +++++++++++++ drivers/common/qat/qat_device.h | 2 ++ drivers/crypto/qat/dev/qat_crypto_pmd_gen3.c | 11 +++++++++++ 3 files changed, 26 insertions(+) diff --git a/drivers/common/qat/qat_device.c b/drivers/common/qat/qat_device.c index f55dc3c6f0..0e7d387d78 100644 --- a/drivers/common/qat/qat_device.c +++ b/drivers/common/qat/qat_device.c @@ -53,6 +53,9 @@ static const struct rte_pci_id pci_id_qat_map[] = { { RTE_PCI_DEVICE(0x8086, 0x18a1), }, + { + RTE_PCI_DEVICE(0x8086, 0x578b), + }, { RTE_PCI_DEVICE(0x8086, 0x4941), }, @@ -194,6 +197,7 @@ pick_gen(const struct rte_pci_device *pci_dev) case 0x18ef: return QAT_GEN2; case 0x18a1: + case 0x578b: return QAT_GEN3; case 0x4941: case 0x4943: @@ -205,6 +209,12 @@ pick_gen(const struct rte_pci_device *pci_dev) } } +static int +wireless_slice_support(uint16_t pci_dev_id) +{ + return pci_dev_id == 0x578b; +} + struct qat_pci_device * qat_pci_device_allocate(struct rte_pci_device *pci_dev, struct qat_dev_cmd_param *qat_dev_cmd_param) @@ -282,6 +292,9 @@ qat_pci_device_allocate(struct rte_pci_device *pci_dev, qat_dev->qat_dev_id = qat_dev_id; qat_dev->qat_dev_gen = qat_dev_gen; + if (wireless_slice_support(pci_dev->id.device_id)) + qat_dev->has_wireless_slice = 1; + ops_hw = qat_dev_hw_spec[qat_dev->qat_dev_gen]; NOT_NULL(ops_hw->qat_dev_get_misc_bar, goto error, "QAT internal error! qat_dev_get_misc_bar function not set"); diff --git a/drivers/common/qat/qat_device.h b/drivers/common/qat/qat_device.h index aa7988bb74..43e4752812 100644 --- a/drivers/common/qat/qat_device.h +++ b/drivers/common/qat/qat_device.h @@ -135,6 +135,8 @@ struct qat_pci_device { /**< Per generation specific information */ uint32_t slice_map; /**< Map of the crypto and compression slices */ + uint16_t has_wireless_slice; + /**< Wireless Slices supported */ }; struct qat_gen_hw_data { diff --git a/drivers/crypto/qat/dev/qat_crypto_pmd_gen3.c b/drivers/crypto/qat/dev/qat_crypto_pmd_gen3.c index 02bcdb06b1..bc53e2e0f1 100644 --- a/drivers/crypto/qat/dev/qat_crypto_pmd_gen3.c +++ b/drivers/crypto/qat/dev/qat_crypto_pmd_gen3.c @@ -255,6 +255,17 @@ qat_sym_crypto_cap_get_gen3(struct qat_cryptodev_private *internals, RTE_CRYPTO_AUTH_SM3_HMAC))) { continue; } + if (internals->qat_dev->has_wireless_slice && ( + check_auth_capa(&capabilities[iter], + RTE_CRYPTO_AUTH_KASUMI_F9) || + check_cipher_capa(&capabilities[iter], + RTE_CRYPTO_CIPHER_KASUMI_F8) || + check_cipher_capa(&capabilities[iter], + RTE_CRYPTO_CIPHER_DES_CBC) || + check_cipher_capa(&capabilities[iter], + RTE_CRYPTO_CIPHER_DES_DOCSISBPI))) + continue; + memcpy(addr + curr_capa, capabilities + iter, sizeof(struct rte_cryptodev_capabilities)); curr_capa++;