From patchwork Thu Dec 7 01:42:02 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jie Hai X-Patchwork-Id: 134895 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 3D3F143692; Thu, 7 Dec 2023 02:46:13 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 243DE42E99; Thu, 7 Dec 2023 02:46:09 +0100 (CET) Received: from szxga08-in.huawei.com (szxga08-in.huawei.com [45.249.212.255]) by mails.dpdk.org (Postfix) with ESMTP id B473F4028B for ; Thu, 7 Dec 2023 02:46:06 +0100 (CET) Received: from kwepemd100004.china.huawei.com (unknown [172.30.72.57]) by szxga08-in.huawei.com (SkyGuard) with ESMTP id 4SlxpY59yPz1Q68T; Thu, 7 Dec 2023 09:42:13 +0800 (CST) Received: from localhost.localdomain (10.67.165.2) by kwepemd100004.china.huawei.com (7.221.188.31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.2.1258.28; Thu, 7 Dec 2023 09:46:01 +0800 From: Jie Hai To: , Yisen Zhuang , Ferruh Yigit , "Min Hu (Connor)" , Chengchang Tang , Hao Chen , "Wei Hu (Xavier)" CC: , , , Subject: [PATCH v2 1/4] net/hns3: fix VF multiple count on one reset Date: Thu, 7 Dec 2023 09:42:02 +0800 Message-ID: <20231207014205.4002558-2-haijie1@huawei.com> X-Mailer: git-send-email 2.30.0 In-Reply-To: <20231207014205.4002558-1-haijie1@huawei.com> References: <20231111015915.2776769-1-haijie1@huawei.com> <20231207014205.4002558-1-haijie1@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.67.165.2] X-ClientProxiedBy: dggems706-chm.china.huawei.com (10.3.19.183) To kwepemd100004.china.huawei.com (7.221.188.31) X-CFilter-Loop: Reflected X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Dengdui Huang There are two ways for the hns3 VF driver to know reset event, namely, interrupt task and periodic detection task. For the latter, the real reset process will delay several microseconds to execute. Both tasks cause the count to increase by 1. However, the periodic detection task also detects a reset event A after interrupt task receive a reset event A. As a result, the reset count will be double. So this patch adds the comparison of reset level for VF in case of the multiple reset count. Fixes: a5475d61fa34 ("net/hns3: support VF") Cc: stable@dpdk.org Signed-off-by: Dengdui Huang Signed-off-by: Jie Hai --- drivers/net/hns3/hns3_ethdev_vf.c | 44 ++++++++++++++++++++----------- 1 file changed, 29 insertions(+), 15 deletions(-) diff --git a/drivers/net/hns3/hns3_ethdev_vf.c b/drivers/net/hns3/hns3_ethdev_vf.c index 916cc0fb1b62..089df146f76e 100644 --- a/drivers/net/hns3/hns3_ethdev_vf.c +++ b/drivers/net/hns3/hns3_ethdev_vf.c @@ -563,13 +563,8 @@ hns3vf_check_event_cause(struct hns3_adapter *hns, uint32_t *clearval) val = hns3_read_dev(hw, HNS3_VF_RST_ING); hns3_write_dev(hw, HNS3_VF_RST_ING, val | HNS3_VF_RST_ING_BIT); val = cmdq_stat_reg & ~BIT(HNS3_VECTOR0_RST_INT_B); - if (clearval) { - hw->reset.stats.global_cnt++; - hns3_warn(hw, "Global reset detected, clear reset status"); - } else { - hns3_schedule_delayed_reset(hns); - hns3_warn(hw, "Global reset detected, don't clear reset status"); - } + hw->reset.stats.global_cnt++; + hns3_warn(hw, "Global reset detected, clear reset status"); ret = HNS3VF_VECTOR0_EVENT_RST; goto out; @@ -584,9 +579,9 @@ hns3vf_check_event_cause(struct hns3_adapter *hns, uint32_t *clearval) val = 0; ret = HNS3VF_VECTOR0_EVENT_OTHER; + out: - if (clearval) - *clearval = val; + *clearval = val; return ret; } @@ -1709,11 +1704,25 @@ is_vf_reset_done(struct hns3_hw *hw) return true; } +static enum hns3_reset_level +hns3vf_detect_reset_event(struct hns3_hw *hw) +{ + enum hns3_reset_level reset = HNS3_NONE_RESET; + uint32_t cmdq_stat_reg; + + cmdq_stat_reg = hns3_read_dev(hw, HNS3_VECTOR0_CMDQ_STAT_REG); + if (BIT(HNS3_VECTOR0_RST_INT_B) & cmdq_stat_reg) + reset = HNS3_VF_RESET; + + return reset; +} + bool hns3vf_is_reset_pending(struct hns3_adapter *hns) { + enum hns3_reset_level last_req; struct hns3_hw *hw = &hns->hw; - enum hns3_reset_level reset; + enum hns3_reset_level new_req; /* * According to the protocol of PCIe, FLR to a PF device resets the PF @@ -1736,13 +1745,18 @@ hns3vf_is_reset_pending(struct hns3_adapter *hns) if (rte_eal_process_type() != RTE_PROC_PRIMARY) return false; - hns3vf_check_event_cause(hns, NULL); - reset = hns3vf_get_reset_level(hw, &hw->reset.pending); - if (hw->reset.level != HNS3_NONE_RESET && reset != HNS3_NONE_RESET && - hw->reset.level < reset) { - hns3_warn(hw, "High level reset %d is pending", reset); + new_req = hns3vf_detect_reset_event(hw); + if (new_req == HNS3_NONE_RESET) + return false; + + last_req = hns3vf_get_reset_level(hw, &hw->reset.pending); + if (last_req == HNS3_NONE_RESET || last_req < new_req) { + __atomic_store_n(&hw->reset.disable_cmd, 1, __ATOMIC_RELAXED); + hns3_schedule_delayed_reset(hns); + hns3_warn(hw, "High level reset detected, delay do reset"); return true; } + return false; }