From patchwork Tue Dec 5 10:00:48 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rakesh Kudurumalla X-Patchwork-Id: 134876 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 96DA143676; Tue, 5 Dec 2023 11:09:00 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 487D9402C8; Tue, 5 Dec 2023 11:09:00 +0100 (CET) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id 4F91C40275 for ; Tue, 5 Dec 2023 11:08:59 +0100 (CET) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 3B5A3qAp012032 for ; Tue, 5 Dec 2023 02:08:56 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=3cNbyc4YwPQlmBnIj3XY9a9taDZ8PNnwR8rjBs95sEs=; b=Dr5IqcRTPkNLXrLTD5A0+H+wACLfmdsu2gF/9LxUuOWPoKinnaZ7gfBI4WDsdXLJF3uX 1r2G/AMvuDudbOg0N7Pbbo/kYgWwiGoZV19UElDcUKsVunXlU8T0oNs7v96mzoxw21pX IwSuHdQZTHvyw9m4+R1ZJaGE1784QPrriLmqkxZyC3Jv/q1QTHhHcv+dOf+yVmMBhNLy caZvM9XSR8aTf1SoQQnzs6N15aGRtxWBXWIHS9GYDpHvMFiepoPjvS/IR+7HOA7kWbgL 53D2jNWI1wkema5j/uRntjfTgus8KxHdPsHxK5OSW6Q/KU119f76qnvLBNOWOHyBp2Db HQ== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3ut0e688h0-4 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Tue, 05 Dec 2023 02:08:50 -0800 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.48; Tue, 5 Dec 2023 02:01:00 -0800 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.48 via Frontend Transport; Tue, 5 Dec 2023 02:01:00 -0800 Received: from localhost.localdomain (unknown [10.28.36.154]) by maili.marvell.com (Postfix) with ESMTP id F2A6C3F7045; Tue, 5 Dec 2023 02:00:57 -0800 (PST) From: Rakesh Kudurumalla To: Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao CC: , , Rakesh Kudurumalla Subject: [PATCH 3/3] net/cnxk: reduce Tx queue release time Date: Tue, 5 Dec 2023 15:30:48 +0530 Message-ID: <20231205100048.1387058-3-rkudurumalla@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20231205100048.1387058-1-rkudurumalla@marvell.com> References: <20231205100048.1387058-1-rkudurumalla@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: ZTYuMBRZRs6yqMMcHCPz1i6BQ4Y2qNDN X-Proofpoint-ORIG-GUID: ZTYuMBRZRs6yqMMcHCPz1i6BQ4Y2qNDN X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.997,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-12-05_04,2023-12-04_01,2023-05-22_02 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Invoked newly added roc API to disable SQB aura FC during TX queue start and TX queue stop. This fix reduces ethdev teardown time Signed-off-by: Rakesh Kudurumalla --- drivers/net/cnxk/cnxk_ethdev.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/net/cnxk/cnxk_ethdev.c b/drivers/net/cnxk/cnxk_ethdev.c index 5e11bbb017..2372a4e793 100644 --- a/drivers/net/cnxk/cnxk_ethdev.c +++ b/drivers/net/cnxk/cnxk_ethdev.c @@ -1521,7 +1521,7 @@ cnxk_nix_tx_queue_start(struct rte_eth_dev *eth_dev, uint16_t qid) if (data->tx_queue_state[qid] == RTE_ETH_QUEUE_STATE_STARTED) return 0; - rc = roc_nix_tm_sq_aura_fc(sq, true); + rc = roc_nix_sq_ena_dis(sq, true); if (rc) { plt_err("Failed to enable sq aura fc, txq=%u, rc=%d", qid, rc); goto done; @@ -1543,7 +1543,7 @@ cnxk_nix_tx_queue_stop(struct rte_eth_dev *eth_dev, uint16_t qid) if (data->tx_queue_state[qid] == RTE_ETH_QUEUE_STATE_STOPPED) return 0; - rc = roc_nix_tm_sq_aura_fc(sq, false); + rc = roc_nix_sq_ena_dis(sq, false); if (rc) { plt_err("Failed to disable sqb aura fc, txq=%u, rc=%d", qid, rc);