From patchwork Fri Oct 27 06:09:46 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jie Hai X-Patchwork-Id: 133478 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id CE60343212; Fri, 27 Oct 2023 08:14:48 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id D23C842DCB; Fri, 27 Oct 2023 08:14:02 +0200 (CEST) Received: from szxga02-in.huawei.com (szxga02-in.huawei.com [45.249.212.188]) by mails.dpdk.org (Postfix) with ESMTP id 85FF0406BA for ; Fri, 27 Oct 2023 08:13:54 +0200 (CEST) Received: from kwepemi500020.china.huawei.com (unknown [172.30.72.57]) by szxga02-in.huawei.com (SkyGuard) with ESMTP id 4SGshF62xjzPnln; Fri, 27 Oct 2023 14:09:49 +0800 (CST) Received: from localhost.localdomain (10.67.165.2) by kwepemi500020.china.huawei.com (7.221.188.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.31; Fri, 27 Oct 2023 14:13:52 +0800 From: Jie Hai To: , Yisen Zhuang , "Wei Hu (Xavier)" , Hongbo Zheng , Hao Chen , Ferruh Yigit , "Min Hu (Connor)" , Chunsong Feng , Huisong Li CC: , , Subject: [PATCH 8/8] net/hns3: refactor interrupt state query Date: Fri, 27 Oct 2023 14:09:46 +0800 Message-ID: <20231027060947.3183983-9-haijie1@huawei.com> X-Mailer: git-send-email 2.30.0 In-Reply-To: <20231027060947.3183983-1-haijie1@huawei.com> References: <20231027060947.3183983-1-haijie1@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.67.165.2] X-ClientProxiedBy: dggems703-chm.china.huawei.com (10.3.19.180) To kwepemi500020.china.huawei.com (7.221.188.8) X-CFilter-Loop: Reflected X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Dengdui Huang PF driver get all interrupt states by reading three registers. This logic code block is distributed in many places. So this patch extracts a common function to do this to improve the maintaince. Fixes: f53a793bb7c2 ("net/hns3: add more hardware error types") Fixes: 3988ab0eee52 ("net/hns3: add abnormal interrupt process") Cc: stable@dpdk.org Signed-off-by: Dengdui Huang --- drivers/net/hns3/hns3_ethdev.c | 57 +++++++++++++++++++--------------- 1 file changed, 32 insertions(+), 25 deletions(-) diff --git a/drivers/net/hns3/hns3_ethdev.c b/drivers/net/hns3/hns3_ethdev.c index bb9dde9c5bc3..0feea52542f6 100644 --- a/drivers/net/hns3/hns3_ethdev.c +++ b/drivers/net/hns3/hns3_ethdev.c @@ -57,6 +57,12 @@ enum hns3_evt_cause { HNS3_VECTOR0_EVENT_OTHER, }; +struct hns3_intr_state { + uint32_t vector0_state; + uint32_t cmdq_state; + uint32_t hw_err_state; +}; + #define HNS3_SPEEDS_SUPP_FEC (RTE_ETH_LINK_SPEED_10G | \ RTE_ETH_LINK_SPEED_25G | \ RTE_ETH_LINK_SPEED_40G | \ @@ -151,20 +157,23 @@ hns3_proc_global_reset_event(struct hns3_adapter *hns, uint32_t *vec_val) return HNS3_VECTOR0_EVENT_RST; } +static void +hns3_query_intr_state(struct hns3_hw *hw, struct hns3_intr_state *state) +{ + state->vector0_state = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG); + state->cmdq_state = hns3_read_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG); + state->hw_err_state = hns3_read_dev(hw, HNS3_RAS_PF_OTHER_INT_STS_REG); +} + static enum hns3_evt_cause hns3_check_event_cause(struct hns3_adapter *hns, uint32_t *clearval) { struct hns3_hw *hw = &hns->hw; - uint32_t vector0_int_stats; - uint32_t cmdq_src_val; - uint32_t hw_err_src_reg; + struct hns3_intr_state state; uint32_t val; enum hns3_evt_cause ret; - /* fetch the events from their corresponding regs */ - vector0_int_stats = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG); - cmdq_src_val = hns3_read_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG); - hw_err_src_reg = hns3_read_dev(hw, HNS3_RAS_PF_OTHER_INT_STS_REG); + hns3_query_intr_state(hw, &state); /* * Assumption: If by any chance reset and mailbox events are reported @@ -173,41 +182,41 @@ hns3_check_event_cause(struct hns3_adapter *hns, uint32_t *clearval) * RX CMDQ event this time we would receive again another interrupt * from H/W just for the mailbox. */ - if (BIT(HNS3_VECTOR0_IMPRESET_INT_B) & vector0_int_stats) { /* IMP */ + if (BIT(HNS3_VECTOR0_IMPRESET_INT_B) & state.vector0_state) { /* IMP */ ret = hns3_proc_imp_reset_event(hns, &val); goto out; } /* Global reset */ - if (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) & vector0_int_stats) { + if (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) & state.vector0_state) { ret = hns3_proc_global_reset_event(hns, &val); goto out; } /* Check for vector0 1588 event source */ - if (BIT(HNS3_VECTOR0_1588_INT_B) & vector0_int_stats) { + if (BIT(HNS3_VECTOR0_1588_INT_B) & state.vector0_state) { val = BIT(HNS3_VECTOR0_1588_INT_B); ret = HNS3_VECTOR0_EVENT_PTP; goto out; } /* check for vector0 msix event source */ - if (vector0_int_stats & HNS3_VECTOR0_REG_MSIX_MASK || - hw_err_src_reg & HNS3_RAS_REG_NFE_MASK) { - val = vector0_int_stats | hw_err_src_reg; + if (state.vector0_state & HNS3_VECTOR0_REG_MSIX_MASK || + state.hw_err_state & HNS3_RAS_REG_NFE_MASK) { + val = state.vector0_state | state.hw_err_state; ret = HNS3_VECTOR0_EVENT_ERR; goto out; } /* check for vector0 mailbox(=CMDQ RX) event source */ - if (BIT(HNS3_VECTOR0_RX_CMDQ_INT_B) & cmdq_src_val) { - cmdq_src_val &= ~BIT(HNS3_VECTOR0_RX_CMDQ_INT_B); - val = cmdq_src_val; + if (BIT(HNS3_VECTOR0_RX_CMDQ_INT_B) & state.cmdq_state) { + state.cmdq_state &= ~BIT(HNS3_VECTOR0_RX_CMDQ_INT_B); + val = state.cmdq_state; ret = HNS3_VECTOR0_EVENT_MBX; goto out; } - val = vector0_int_stats; + val = state.vector0_state; ret = HNS3_VECTOR0_EVENT_OTHER; out: @@ -346,10 +355,8 @@ hns3_interrupt_handler(void *param) struct hns3_adapter *hns = dev->data->dev_private; struct hns3_hw *hw = &hns->hw; enum hns3_evt_cause event_cause; + struct hns3_intr_state state; uint32_t clearval = 0; - uint32_t vector0_int; - uint32_t ras_int; - uint32_t cmdq_int; if (!hns3_reset_event_valid(hw)) return; @@ -358,16 +365,15 @@ hns3_interrupt_handler(void *param) hns3_pf_disable_irq0(hw); event_cause = hns3_check_event_cause(hns, &clearval); - vector0_int = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG); - ras_int = hns3_read_dev(hw, HNS3_RAS_PF_OTHER_INT_STS_REG); - cmdq_int = hns3_read_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG); + hns3_query_intr_state(hw, &state); hns3_delay_before_clear_event_cause(hw, event_cause, clearval); hns3_clear_event_cause(hw, event_cause, clearval); /* vector 0 interrupt is shared with reset and mailbox source events. */ if (event_cause == HNS3_VECTOR0_EVENT_ERR) { hns3_warn(hw, "received interrupt: vector0_int_stat:0x%x " "ras_int_stat:0x%x cmdq_int_stat:0x%x", - vector0_int, ras_int, cmdq_int); + state.vector0_state, state.hw_err_state, + state.cmdq_state); hns3_handle_mac_tnl(hw); hns3_handle_error(hns); } else if (event_cause == HNS3_VECTOR0_EVENT_RST) { @@ -378,7 +384,8 @@ hns3_interrupt_handler(void *param) } else if (event_cause != HNS3_VECTOR0_EVENT_PTP) { hns3_warn(hw, "received unknown event: vector0_int_stat:0x%x " "ras_int_stat:0x%x cmdq_int_stat:0x%x", - vector0_int, ras_int, cmdq_int); + state.vector0_state, state.hw_err_state, + state.cmdq_state); } /* Enable interrupt if it is not cause by reset */