From patchwork Mon Oct 16 15:10:55 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pavan Nikhilesh Bhagavatula X-Patchwork-Id: 132635 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 4F5A64317F; Mon, 16 Oct 2023 17:11:16 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id CA4FC402CB; Mon, 16 Oct 2023 17:11:15 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id A142140269 for ; Mon, 16 Oct 2023 17:11:14 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 39G9guE5013098 for ; Mon, 16 Oct 2023 08:11:13 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=G4afx2XEKTFuLcO63lVyiY4IEiirAuJC9OgcbKB4MDw=; b=JLk9MyGDe9bs7ut1AAFMr3c0U43I1f2Op+Z/4eM9zmmckbCVPzaMvgJ11QZQXTIdsZ66 amyhhD/i2R0dkPgxmRT3Fkdl9v+V3cnE2ccudJdkxKOc76/M0MJtDRDrbG4EoRMojXyc tPUGtLxLvMOE2ZGwSYrar/4EnRAddESO3Ka4jEZBhwU3N7JBJIbg/Bkyg7RYYDNTpgey oGqwzNJm28ZUesRdfav6Nz8M9nP7FELqZt8kMRIXRrKf3EfmLtRotBRi26s3nOcEEDJ7 JavUxoSjVjspFH4dOE/GDLP6bJi1BlswqdVZ+O2UdOBWbHnolTUFjy5mP/3498Uq6fb0 5w== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3ts2skh2mt-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Mon, 16 Oct 2023 08:11:12 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.48; Mon, 16 Oct 2023 08:10:59 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.48 via Frontend Transport; Mon, 16 Oct 2023 08:10:59 -0700 Received: from MININT-80QBFE8.corp.innovium.com (MININT-80QBFE8.marvell.com [10.28.164.106]) by maili.marvell.com (Postfix) with ESMTP id CC9983F70A8; Mon, 16 Oct 2023 08:10:57 -0700 (PDT) From: To: , Pavan Nikhilesh , "Shijith Thotton" CC: Subject: [PATCH] event/cnxk: update fc check to use SQEs Date: Mon, 16 Oct 2023 20:40:55 +0530 Message-ID: <20231016151055.2436-1-pbhagavatula@marvell.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-Proofpoint-GUID: P4Px-QzdL9UWUqjp-1lMDhVPLOc3E44s X-Proofpoint-ORIG-GUID: P4Px-QzdL9UWUqjp-1lMDhVPLOc3E44s X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.980,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-10-16_09,2023-10-12_01,2023-05-22_02 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Pavan Nikhilesh Update fc check to count SQEs instead of SQBs while waiting for space. Signed-off-by: Pavan Nikhilesh --- drivers/event/cnxk/cn10k_tx_worker.h | 33 ++++++++++++++++++---------- drivers/event/cnxk/cn9k_worker.h | 33 +++++++++++++++++++++++++--- 2 files changed, 51 insertions(+), 15 deletions(-) diff --git a/drivers/event/cnxk/cn10k_tx_worker.h b/drivers/event/cnxk/cn10k_tx_worker.h index dea6cdcde2..53e0dde20c 100644 --- a/drivers/event/cnxk/cn10k_tx_worker.h +++ b/drivers/event/cnxk/cn10k_tx_worker.h @@ -24,26 +24,35 @@ cn10k_sso_hws_xtract_meta(struct rte_mbuf *m, const uint64_t *txq_data) static __rte_always_inline void cn10k_sso_txq_fc_wait(const struct cn10k_eth_txq *txq) { + int64_t avail; + #ifdef RTE_ARCH_ARM64 - uint64_t space; + int64_t val; asm volatile(PLT_CPU_FEATURE_PREAMBLE - " ldxr %[space], [%[addr]] \n" - " cmp %[adj], %[space] \n" - " b.hi .Ldne%= \n" + " ldxr %[val], [%[addr]] \n" + " sub %[val], %[adj], %[val] \n" + " lsl %[refill], %[val], %[shft] \n" + " sub %[refill], %[refill], %[val] \n" + " cmp %[refill], #0x0 \n" + " b.gt .Ldne%= \n" " sevl \n" ".Lrty%=: wfe \n" - " ldxr %[space], [%[addr]] \n" - " cmp %[adj], %[space] \n" - " b.ls .Lrty%= \n" + " ldxr %[val], [%[addr]] \n" + " sub %[val], %[adj], %[val] \n" + " lsl %[refill], %[val], %[shft] \n" + " sub %[refill], %[refill], %[val] \n" + " cmp %[refill], #0x0 \n" + " b.le .Lrty%= \n" ".Ldne%=: \n" - : [space] "=&r"(space) - : [adj] "r"(txq->nb_sqb_bufs_adj), [addr] "r"(txq->fc_mem) + : [refill] "=&r"(avail), [val] "=&r" (val) + : [addr] "r"(txq->fc_mem), [adj] "r"(txq->nb_sqb_bufs_adj), + [shft] "r"(txq->sqes_per_sqb_log2) : "memory"); #else - while ((uint64_t)txq->nb_sqb_bufs_adj <= - __atomic_load_n(txq->fc_mem, __ATOMIC_RELAXED)) - ; + do { + avail = txq->nb_sqb_bufs_adj - __atomic_load_n(txq->fc_mem, __ATOMIC_RELAXED); + } while (((avail << txq->sqes_per_sqb_log2) - avail) <= 0); #endif } diff --git a/drivers/event/cnxk/cn9k_worker.h b/drivers/event/cnxk/cn9k_worker.h index 6936b7ad04..0451157812 100644 --- a/drivers/event/cnxk/cn9k_worker.h +++ b/drivers/event/cnxk/cn9k_worker.h @@ -542,9 +542,36 @@ NIX_RX_FASTPATH_MODES static __rte_always_inline void cn9k_sso_txq_fc_wait(const struct cn9k_eth_txq *txq) { - while ((uint64_t)txq->nb_sqb_bufs_adj <= - __atomic_load_n(txq->fc_mem, __ATOMIC_RELAXED)) - ; + int64_t avail; + +#ifdef RTE_ARCH_ARM64 + int64_t val; + + asm volatile(PLT_CPU_FEATURE_PREAMBLE + " ldxr %[val], [%[addr]] \n" + " sub %[val], %[adj], %[val] \n" + " lsl %[refill], %[val], %[shft] \n" + " sub %[refill], %[refill], %[val] \n" + " cmp %[refill], #0x0 \n" + " b.gt .Ldne%= \n" + " sevl \n" + ".Lrty%=: wfe \n" + " ldxr %[val], [%[addr]] \n" + " sub %[val], %[adj], %[val] \n" + " lsl %[refill], %[val], %[shft] \n" + " sub %[refill], %[refill], %[val] \n" + " cmp %[refill], #0x0 \n" + " b.le .Lrty%= \n" + ".Ldne%=: \n" + : [refill] "=&r"(avail), [val] "=&r" (val) + : [addr] "r"(txq->fc_mem), [adj] "r"(txq->nb_sqb_bufs_adj), + [shft] "r"(txq->sqes_per_sqb_log2) + : "memory"); +#else + do { + avail = txq->nb_sqb_bufs_adj - __atomic_load_n(txq->fc_mem, __ATOMIC_RELAXED); + } while (((avail << txq->sqes_per_sqb_log2) - avail) <= 0); +#endif } static __rte_always_inline struct cn9k_eth_txq *