From patchwork Fri Oct 13 16:35:48 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ashwin Sekhar T K X-Patchwork-Id: 132609 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 960F143158; Fri, 13 Oct 2023 18:35:59 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 6AD75402CC; Fri, 13 Oct 2023 18:35:59 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id 0B06C4027D for ; Fri, 13 Oct 2023 18:35:57 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 39DCqKMM010077 for ; Fri, 13 Oct 2023 09:35:57 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=hRjpfIsEtRJGS0uZerc8XX1ICHHjyE8Ke6CQhyBIjPI=; b=AXrguhN6/XwuxDM5VvdfLXaMELbHQGAHxfpH/oHb3YyKDhpqZ4zLQARkZUYhviyTjof1 0UCTt4EEzwM+TehwEMJs7dRwOv4O6dlKE2G2zMW+6DilsI4D4MLFYT9hB95PuQQVd11m 4nOgg/SUTXhvZbFd4SHQDPKNo0NoY0X2k6LhTSXLwrQFHJSdtDnwJeJ/Ev6RUOE9nnyx lXbBQaHP6o2Q1EFWH5XcZCNp2wlZ+GvFHB5pDCkwSI8tEKLAAW7XkRDhqQzTilVbUm98 9leiprQZgJ4oXyEOpaGDavgq/hkFBFzwLfrsm+9+T+HVr86sWRMKGGxTRIgmbggKYO6Q uw== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3tpt16k1yg-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Fri, 13 Oct 2023 09:35:57 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.48; Fri, 13 Oct 2023 09:35:55 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.48 via Frontend Transport; Fri, 13 Oct 2023 09:35:55 -0700 Received: from localhost.localdomain (unknown [10.28.36.142]) by maili.marvell.com (Postfix) with ESMTP id 646693F707E; Fri, 13 Oct 2023 09:35:51 -0700 (PDT) From: Ashwin Sekhar T K To: , Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao CC: , , , , , , , Kommula Shiva Shankar Subject: [PATCH] common/cnxk: fix pool buffer size in opaque mode Date: Fri, 13 Oct 2023 22:05:48 +0530 Message-ID: <20231013163548.2226503-1-asekhar@marvell.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-Proofpoint-GUID: nfA7GJtaOJnss0e4lUjTc3KFQnDAmrSq X-Proofpoint-ORIG-GUID: nfA7GJtaOJnss0e4lUjTc3KFQnDAmrSq X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.980,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-10-13_07,2023-10-12_01,2023-05-22_02 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Kommula Shiva Shankar Pool buffer size in opaque mode must always be set to 0. Fixes: f765f5611240 ("common/cnxk: add NPA pool HW operations") Signed-off-by: Kommula Shiva Shankar Signed-off-by: Ashwin Sekhar T K Acked-by: Jerin Jacob --- drivers/common/cnxk/roc_npa.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/common/cnxk/roc_npa.c b/drivers/common/cnxk/roc_npa.c index b76b8e2342..6c14c49901 100644 --- a/drivers/common/cnxk/roc_npa.c +++ b/drivers/common/cnxk/roc_npa.c @@ -517,7 +517,11 @@ npa_aura_pool_pair_alloc(struct npa_lf *lf, const uint32_t block_size, /* Update pool fields */ pool->stack_base = mz->iova; pool->ena = 1; - pool->buf_size = block_size / ROC_ALIGN; + /* In opaque mode buffer size must be 0 */ + if (!pool->nat_align) + pool->buf_size = 0; + else + pool->buf_size = block_size / ROC_ALIGN; pool->stack_max_pages = stack_size; pool->shift = plt_log2_u32(block_count); pool->shift = pool->shift < 8 ? 0 : pool->shift - 8;