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dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.161 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.161; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.161) by CY4PEPF0000EDD1.mail.protection.outlook.com (10.167.241.205) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6838.22 via Frontend Transport; Wed, 11 Oct 2023 06:43:52 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.67) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.41; Tue, 10 Oct 2023 23:43:40 -0700 Received: from nvidia.com (10.126.230.35) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.41; Tue, 10 Oct 2023 23:43:38 -0700 From: Jiawei Wang To: , CC: , , Subject: [PATCH] net/mlx5: fix the E-Switch mirror flow rule validation Date: Wed, 11 Oct 2023 09:43:19 +0300 Message-ID: <20231011064319.41817-1-jiaweiw@nvidia.com> X-Mailer: git-send-email 2.18.1 MIME-Version: 1.0 X-Originating-IP: [10.126.230.35] X-ClientProxiedBy: rnnvmail202.nvidia.com (10.129.68.7) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000EDD1:EE_|MN2PR12MB4341:EE_ X-MS-Office365-Filtering-Correlation-Id: 05909490-895c-4140-8c7d-08dbca256f36 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 Oct 2023 06:43:52.9941 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 05909490-895c-4140-8c7d-08dbca256f36 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000EDD1.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB4341 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org The port action and jump to flow table action are not supported in the mirror flows (RTE_FLOW_ACTION_TYPE_SAMPLE with sample ratio=1) in E-Switch domain (transfer attribute set) without presented encap action. The encap action is supported for uplink port only. So, if flow with mirroring contains encap action application should provide encap and uplink port actions in the mirror action list and PMD validates this condition (to make sure we cover the hardware limitation). This patch adds the validation for E-Switch mirror flow rule checking and rejects as invalid. Fixes: 6a951567c159 ("net/mlx5: support E-Switch mirroring and jump in one flow") Cc: stable@dpdk.org Signed-off-by: Jiawei Wang Acked-by: Ori Kam --- doc/guides/nics/mlx5.rst | 5 ++ drivers/net/mlx5/mlx5_flow_dv.c | 93 +++++++++++++++++++++++++-------- 2 files changed, 76 insertions(+), 22 deletions(-) diff --git a/doc/guides/nics/mlx5.rst b/doc/guides/nics/mlx5.rst index 7bee57d9dd..16c322578a 100644 --- a/doc/guides/nics/mlx5.rst +++ b/doc/guides/nics/mlx5.rst @@ -545,6 +545,11 @@ Limitations sample actions list. - For E-Switch mirroring flow, supports ``RAW ENCAP``, ``Port ID``, ``VXLAN ENCAP``, ``NVGRE ENCAP`` in the sample actions list. + - For E-Switch mirroring flow with sample ratio = 1, the ``ENCAP`` action + support for uplink port only. + - For E-Switch mirroring flow with sample ratio = 1, the ``PORT`` action and + ``JUMP`` action are not supported without presented ``ENCAP`` action in the + sample actions list. - For ConnectX-5 trusted device, the application metadata with SET_TAG index 0 is not supported before ``RTE_FLOW_ACTION_TYPE_SAMPLE`` action. diff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c index 3dc2fe5c71..8c9a00ef85 100644 --- a/drivers/net/mlx5/mlx5_flow_dv.c +++ b/drivers/net/mlx5/mlx5_flow_dv.c @@ -6029,6 +6029,7 @@ flow_dv_modify_clone_free_cb(void *tool_ctx, struct mlx5_list_entry *entry) */ static int flow_dv_validate_action_sample(uint64_t *action_flags, + uint64_t *sub_action_flags, const struct rte_flow_action *action, struct rte_eth_dev *dev, const struct rte_flow_attr *attr, @@ -6037,14 +6038,15 @@ flow_dv_validate_action_sample(uint64_t *action_flags, const struct rte_flow_action_rss **sample_rss, const struct rte_flow_action_count **count, int *fdb_mirror, + uint16_t *sample_port_id, bool root, struct rte_flow_error *error) { struct mlx5_priv *priv = dev->data->dev_private; struct mlx5_sh_config *dev_conf = &priv->sh->config; const struct rte_flow_action_sample *sample = action->conf; + const struct rte_flow_action_port_id *port = NULL; const struct rte_flow_action *act; - uint64_t sub_action_flags = 0; uint16_t queue_index = 0xFFFF; int actions_n = 0; int ret; @@ -6091,20 +6093,20 @@ flow_dv_validate_action_sample(uint64_t *action_flags, switch (act->type) { case RTE_FLOW_ACTION_TYPE_QUEUE: ret = mlx5_flow_validate_action_queue(act, - sub_action_flags, + *sub_action_flags, dev, attr, error); if (ret < 0) return ret; queue_index = ((const struct rte_flow_action_queue *) (act->conf))->index; - sub_action_flags |= MLX5_FLOW_ACTION_QUEUE; + *sub_action_flags |= MLX5_FLOW_ACTION_QUEUE; ++actions_n; break; case RTE_FLOW_ACTION_TYPE_RSS: *sample_rss = act->conf; ret = mlx5_flow_validate_action_rss(act, - sub_action_flags, + *sub_action_flags, dev, attr, item_flags, error); @@ -6120,48 +6122,57 @@ flow_dv_validate_action_sample(uint64_t *action_flags, "or level in the same flow"); if (*sample_rss != NULL && (*sample_rss)->queue_num) queue_index = (*sample_rss)->queue[0]; - sub_action_flags |= MLX5_FLOW_ACTION_RSS; + *sub_action_flags |= MLX5_FLOW_ACTION_RSS; ++actions_n; break; case RTE_FLOW_ACTION_TYPE_MARK: ret = flow_dv_validate_action_mark(dev, act, - sub_action_flags, + *sub_action_flags, attr, error); if (ret < 0) return ret; if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) - sub_action_flags |= MLX5_FLOW_ACTION_MARK | + *sub_action_flags |= MLX5_FLOW_ACTION_MARK | MLX5_FLOW_ACTION_MARK_EXT; else - sub_action_flags |= MLX5_FLOW_ACTION_MARK; + *sub_action_flags |= MLX5_FLOW_ACTION_MARK; ++actions_n; break; case RTE_FLOW_ACTION_TYPE_COUNT: ret = flow_dv_validate_action_count - (dev, false, *action_flags | sub_action_flags, + (dev, false, *action_flags | *sub_action_flags, root, error); if (ret < 0) return ret; *count = act->conf; - sub_action_flags |= MLX5_FLOW_ACTION_COUNT; + *sub_action_flags |= MLX5_FLOW_ACTION_COUNT; *action_flags |= MLX5_FLOW_ACTION_COUNT; ++actions_n; break; case RTE_FLOW_ACTION_TYPE_PORT_ID: case RTE_FLOW_ACTION_TYPE_REPRESENTED_PORT: ret = flow_dv_validate_action_port_id(dev, - sub_action_flags, + *sub_action_flags, act, attr, error); if (ret) return ret; - sub_action_flags |= MLX5_FLOW_ACTION_PORT_ID; + if (act->type == RTE_FLOW_ACTION_TYPE_PORT_ID) { + port = (const struct rte_flow_action_port_id *) + act->conf; + *sample_port_id = port->original ? + dev->data->port_id : port->id; + } else { + *sample_port_id = ((const struct rte_flow_action_ethdev *) + act->conf)->port_id; + } + *sub_action_flags |= MLX5_FLOW_ACTION_PORT_ID; ++actions_n; break; case RTE_FLOW_ACTION_TYPE_RAW_ENCAP: ret = flow_dv_validate_action_raw_encap_decap - (dev, NULL, act->conf, attr, &sub_action_flags, + (dev, NULL, act->conf, attr, sub_action_flags, &actions_n, action, item_flags, error); if (ret < 0) return ret; @@ -6170,12 +6181,12 @@ flow_dv_validate_action_sample(uint64_t *action_flags, case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP: case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP: ret = flow_dv_validate_action_l2_encap(dev, - sub_action_flags, + *sub_action_flags, act, attr, error); if (ret < 0) return ret; - sub_action_flags |= MLX5_FLOW_ACTION_ENCAP; + *sub_action_flags |= MLX5_FLOW_ACTION_ENCAP; ++actions_n; break; default: @@ -6187,7 +6198,7 @@ flow_dv_validate_action_sample(uint64_t *action_flags, } } if (attr->ingress) { - if (!(sub_action_flags & (MLX5_FLOW_ACTION_QUEUE | + if (!(*sub_action_flags & (MLX5_FLOW_ACTION_QUEUE | MLX5_FLOW_ACTION_RSS))) return rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION, @@ -6209,17 +6220,17 @@ flow_dv_validate_action_sample(uint64_t *action_flags, "E-Switch doesn't support " "any optional action " "for sampling"); - if (sub_action_flags & MLX5_FLOW_ACTION_QUEUE) + if (*sub_action_flags & MLX5_FLOW_ACTION_QUEUE) return rte_flow_error_set(error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ACTION, NULL, "unsupported action QUEUE"); - if (sub_action_flags & MLX5_FLOW_ACTION_RSS) + if (*sub_action_flags & MLX5_FLOW_ACTION_RSS) return rte_flow_error_set(error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ACTION, NULL, "unsupported action QUEUE"); - if (!(sub_action_flags & MLX5_FLOW_ACTION_PORT_ID)) + if (!(*sub_action_flags & MLX5_FLOW_ACTION_PORT_ID)) return rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION, NULL, @@ -6228,16 +6239,16 @@ flow_dv_validate_action_sample(uint64_t *action_flags, *fdb_mirror = 1; } /* Continue validation for Xcap actions.*/ - if ((sub_action_flags & MLX5_FLOW_XCAP_ACTIONS) && + if ((*sub_action_flags & MLX5_FLOW_XCAP_ACTIONS) && (queue_index == 0xFFFF || !mlx5_rxq_is_hairpin(dev, queue_index))) { - if ((sub_action_flags & MLX5_FLOW_XCAP_ACTIONS) == + if ((*sub_action_flags & MLX5_FLOW_XCAP_ACTIONS) == MLX5_FLOW_XCAP_ACTIONS) return rte_flow_error_set(error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ACTION, NULL, "encap and decap " "combination aren't " "supported"); - if (attr->ingress && (sub_action_flags & MLX5_FLOW_ACTION_ENCAP)) + if (attr->ingress && (*sub_action_flags & MLX5_FLOW_ACTION_ENCAP)) return rte_flow_error_set(error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ACTION, NULL, "encap is not supported" @@ -7392,9 +7403,14 @@ flow_dv_validate(struct rte_eth_dev *dev, const struct rte_flow_attr *attr, uint32_t tag_id = 0, tag_bitmap = 0; const struct rte_flow_action_age *non_shared_age = NULL; const struct rte_flow_action_count *count = NULL; + const struct rte_flow_action_port_id *port = NULL; const struct mlx5_rte_flow_item_tag *mlx5_tag; struct mlx5_priv *act_priv = NULL; int aso_after_sample = 0; + struct mlx5_priv *port_priv = NULL; + uint64_t sub_action_flags = 0; + uint16_t sample_port_id = 0; + uint16_t port_id = 0; if (items == NULL) return -1; @@ -7864,6 +7880,14 @@ flow_dv_validate(struct rte_eth_dev *dev, const struct rte_flow_attr *attr, error); if (ret) return ret; + if (type == RTE_FLOW_ACTION_TYPE_PORT_ID) { + port = (const struct rte_flow_action_port_id *) + actions->conf; + port_id = port->original ? dev->data->port_id : port->id; + } else { + port_id = ((const struct rte_flow_action_ethdev *) + actions->conf)->port_id; + } action_flags |= MLX5_FLOW_ACTION_PORT_ID; ++actions_n; break; @@ -8363,11 +8387,13 @@ flow_dv_validate(struct rte_eth_dev *dev, const struct rte_flow_attr *attr, break; case RTE_FLOW_ACTION_TYPE_SAMPLE: ret = flow_dv_validate_action_sample(&action_flags, + &sub_action_flags, actions, dev, attr, item_flags, rss, &sample_rss, &sample_count, &fdb_mirror, + &sample_port_id, is_root, error); if (ret < 0) @@ -8679,6 +8705,29 @@ flow_dv_validate(struct rte_eth_dev *dev, const struct rte_flow_attr *attr, return rte_flow_error_set(error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ACTION, NULL, "sample before ASO action is not supported"); + if (sub_action_flags & MLX5_FLOW_ACTION_PORT_ID) { + port_priv = mlx5_port_to_eswitch_info(sample_port_id, false); + if (flow_source_vport_representor(priv, port_priv)) { + if (sub_action_flags & MLX5_FLOW_ACTION_ENCAP) + return rte_flow_error_set(error, ENOTSUP, + RTE_FLOW_ERROR_TYPE_ACTION, NULL, + "mirror to rep port with encap is not supported"); + } else { + if ((sub_action_flags & ~MLX5_FLOW_ACTION_ENCAP) && + (action_flags & MLX5_FLOW_ACTION_JUMP)) + return rte_flow_error_set(error, ENOTSUP, + RTE_FLOW_ERROR_TYPE_ACTION, NULL, + "mirror to wire port without encap is not supported"); + } + } + if ((action_flags & MLX5_FLOW_ACTION_PORT_ID) && + (action_flags & MLX5_FLOW_ACTION_ENCAP)) { + port_priv = mlx5_port_to_eswitch_info(port_id, false); + if (flow_source_vport_representor(priv, port_priv)) + return rte_flow_error_set(error, ENOTSUP, + RTE_FLOW_ERROR_TYPE_ACTION, NULL, + "mirror to rep port with encap is not supported"); + } } /* * Validation the NIC Egress flow on representor, except implicit