From patchwork Thu Sep 21 20:43:46 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Chautru, Nicolas" X-Patchwork-Id: 131811 X-Patchwork-Delegate: maxime.coquelin@redhat.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id A13204260E; Thu, 21 Sep 2023 22:47:25 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 8807740698; Thu, 21 Sep 2023 22:47:04 +0200 (CEST) Received: from mgamail.intel.com (mgamail.intel.com [134.134.136.100]) by mails.dpdk.org (Postfix) with ESMTP id 2E8F8402D3 for ; Thu, 21 Sep 2023 22:47:00 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1695329220; x=1726865220; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=SR7Ym7ak1Kx5RG2tkmL06qIMNUIaqtKYAqZ+woGT5Hg=; b=mqQCuVGTkn+zOD8LYm00Ubt3tFRGqCe30dodlDQS+g23AkMA77o6PVia m5aDYkrATJq3lbelDI1w64FcQLWan1wjIlgS1BZnOeB1keKZFYh5XWrO9 vZGzBzYOEoegvUqQOwIxaDSUa/PcB+KXMUDPa1iPh/W/RbK1cm9g7/mG5 WzPSql34J6FovcN518qgkuo6ue+uVF5TvgUQVvwcIOi4241GGrTHYTZxp ZxwW+9Gmd1513IcTp2RGIKeWPUaB6zYns/MjSRG+TXOFgCRSDupi2cuhR h67yShOvsJ+Sc3Bq+MGezCTXrqMihOD0A8EpP/d2DETK+TYtnRpQAG1R5 A==; X-IronPort-AV: E=McAfee;i="6600,9927,10840"; a="447138113" X-IronPort-AV: E=Sophos;i="6.03,166,1694761200"; d="scan'208";a="447138113" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Sep 2023 13:46:59 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10840"; a="696907254" X-IronPort-AV: E=Sophos;i="6.03,166,1694761200"; d="scan'208";a="696907254" Received: from spr-npg-bds1-eec2.sn.intel.com (HELO spr-npg-bds1-eec2..) ([10.233.181.123]) by orsmga003.jf.intel.com with ESMTP; 21 Sep 2023 13:46:59 -0700 From: Nicolas Chautru To: dev@dpdk.org, maxime.coquelin@redhat.com Cc: hemant.agrawal@nxp.com, david.marchand@redhat.com, hernan.vargas@intel.com, Nicolas Chautru Subject: [PATCH v2 4/7] baseband/acc: allocate FCW memory separately Date: Thu, 21 Sep 2023 20:43:46 +0000 Message-Id: <20230921204349.3285318-5-nicolas.chautru@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230921204349.3285318-1-nicolas.chautru@intel.com> References: <20230921204349.3285318-1-nicolas.chautru@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org This allows more flexibility to the FCW size for the unified driver. No actual functional change. Signed-off-by: Nicolas Chautru --- drivers/baseband/acc/acc_common.h | 4 +++- drivers/baseband/acc/rte_vrb_pmd.c | 25 ++++++++++++++++++++++++- 2 files changed, 27 insertions(+), 2 deletions(-) diff --git a/drivers/baseband/acc/acc_common.h b/drivers/baseband/acc/acc_common.h index df18506e75..b5ee113faf 100644 --- a/drivers/baseband/acc/acc_common.h +++ b/drivers/baseband/acc/acc_common.h @@ -101,6 +101,7 @@ #define ACC_NUM_QGRPS_PER_WORD 8 #define ACC_MAX_NUM_QGRPS 32 #define ACC_RING_SIZE_GRANULARITY 64 +#define ACC_MAX_FCW_SIZE 128 /* Constants from K0 computation from 3GPP 38.212 Table 5.4.2.1-2 */ #define ACC_N_ZC_1 66 /* N = 66 Zc for BG 1 */ @@ -582,13 +583,14 @@ struct __rte_cache_aligned acc_queue { uint32_t aq_enqueued; /* Count how many "batches" have been enqueued */ uint32_t aq_dequeued; /* Count how many "batches" have been dequeued */ uint32_t irq_enable; /* Enable ops dequeue interrupts if set to 1 */ - struct rte_mempool *fcw_mempool; /* FCW mempool */ enum rte_bbdev_op_type op_type; /* Type of this Queue: TE or TD */ /* Internal Buffers for loopback input */ uint8_t *lb_in; uint8_t *lb_out; + uint8_t *fcw_ring; rte_iova_t lb_in_addr_iova; rte_iova_t lb_out_addr_iova; + rte_iova_t fcw_ring_addr_iova; int8_t *derm_buffer; /* interim buffer for de-rm in SDK */ struct acc_device *d; }; diff --git a/drivers/baseband/acc/rte_vrb_pmd.c b/drivers/baseband/acc/rte_vrb_pmd.c index 6898a0f802..f460e9ea2a 100644 --- a/drivers/baseband/acc/rte_vrb_pmd.c +++ b/drivers/baseband/acc/rte_vrb_pmd.c @@ -883,6 +883,25 @@ vrb_queue_setup(struct rte_bbdev *dev, uint16_t queue_id, goto free_companion_ring_addr; } + q->fcw_ring = rte_zmalloc_socket(dev->device->driver->name, + ACC_MAX_FCW_SIZE * d->sw_ring_max_depth, + RTE_CACHE_LINE_SIZE, conf->socket); + if (q->fcw_ring == NULL) { + rte_bbdev_log(ERR, "Failed to allocate fcw_ring memory"); + ret = -ENOMEM; + goto free_companion_ring_addr; + } + q->fcw_ring_addr_iova = rte_malloc_virt2iova(q->fcw_ring); + + /* For FFT we need to store the FCW separately */ + if (conf->op_type == RTE_BBDEV_OP_FFT) { + for (desc_idx = 0; desc_idx < d->sw_ring_max_depth; desc_idx++) { + desc = q->ring_addr + desc_idx; + desc->req.data_ptrs[0].address = q->fcw_ring_addr_iova + + desc_idx * ACC_MAX_FCW_SIZE; + } + } + q->qgrp_id = (q_idx >> VRB1_GRP_ID_SHIFT) & 0xF; q->vf_id = (q_idx >> VRB1_VF_ID_SHIFT) & 0x3F; q->aq_id = q_idx & 0xF; @@ -994,6 +1013,7 @@ vrb_queue_release(struct rte_bbdev *dev, uint16_t q_id) if (q != NULL) { /* Mark the Queue as un-assigned. */ d->q_assigned_bit_map[q->qgrp_id] &= (~0ULL - (1 << (uint64_t) q->aq_id)); + rte_free(q->fcw_ring); rte_free(q->companion_ring_addr); rte_free(q->lb_in); rte_free(q->lb_out); @@ -3224,7 +3244,10 @@ vrb_enqueue_fft_one_op(struct acc_queue *q, struct rte_bbdev_fft_op *op, output = op->fft.base_output.data; in_offset = op->fft.base_input.offset; out_offset = op->fft.base_output.offset; - fcw = &desc->req.fcw_fft; + + fcw = (struct acc_fcw_fft *) (q->fcw_ring + + ((q->sw_ring_head + total_enqueued_cbs) & q->sw_ring_wrap_mask) + * ACC_MAX_FCW_SIZE); vrb1_fcw_fft_fill(op, fcw); vrb1_dma_desc_fft_fill(op, &desc->req, input, output, &in_offset, &out_offset);