From patchwork Fri Aug 25 10:13:39 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simei Su X-Patchwork-Id: 130759 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 56916430FF; Fri, 25 Aug 2023 12:14:57 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id D47D443280; Fri, 25 Aug 2023 12:14:20 +0200 (CEST) Received: from mgamail.intel.com (mgamail.intel.com [134.134.136.100]) by mails.dpdk.org (Postfix) with ESMTP id 3AF7B43288 for ; Fri, 25 Aug 2023 12:14:16 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1692958456; x=1724494456; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=THcs0Z3xg1j7y02r6qCWgcTN+NoUGPdfZGxoY6MV+8I=; b=WeijX2WMa4vILWgg21DMB+PM3pELbw/HFGoU3BU3yt4/za0HcvicxSTg Ptc8csunHWzjox+FycLZhYefRb5sDu/+P1QY8719wNYlLci3Lt580kI9u DiZkzdCareEnKJHfv5ZKZFa6MlHmtpj2rHdqG0l2O7uoF9uknAdqtBySM xuJna2quNZBqfqHPBCweCkY8JNwJE1ezThIOolcJda01cnFZwVed8a40Q aYBd5j30JSGA8bXDpVEJGU7BgQJTP4niRIuxjqmoais/faVMvYzc9IXP/ yvLgOUzr+jj+WFiy06E7cyuEc6PE74wk8ZG1eAeLhCvPF7475EXtCio79 A==; X-IronPort-AV: E=McAfee;i="6600,9927,10812"; a="441028083" X-IronPort-AV: E=Sophos;i="6.02,195,1688454000"; d="scan'208";a="441028083" Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Aug 2023 03:14:15 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10812"; a="772439748" X-IronPort-AV: E=Sophos;i="6.02,195,1688454000"; d="scan'208";a="772439748" Received: from dpdk-simei-icelake.sh.intel.com ([10.67.110.167]) by orsmga001.jf.intel.com with ESMTP; 25 Aug 2023 03:14:13 -0700 From: Simei Su To: jingjing.wu@intel.com, beilei.xing@intel.com, qi.z.zhang@intel.com Cc: dev@dpdk.org, mingxia.liu@intel.com, wenjing.qiao@intel.com, Simei Su , Pavan Kumar Linga Subject: [PATCH v2 12/17] common/idpf/base: refine comments and alignment Date: Fri, 25 Aug 2023 18:13:39 +0800 Message-Id: <20230825101344.1828774-13-simei.su@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230825101344.1828774-1-simei.su@intel.com> References: <20230809013308.1449103-1-wenjing.qiao@intel.com> <20230825101344.1828774-1-simei.su@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Refine the macros and definitions by using 'tab' spaces and new lines wherever necessary. Also refine the comment in 'idpf_ctlq_setup_regs' and remove the TODO comment in idpf_rss_hash enum as it doesn't make any sense. Signed-off-by: Pavan Kumar Linga Signed-off-by: Simei Su --- drivers/common/idpf/base/idpf_controlq.c | 2 +- drivers/common/idpf/base/idpf_controlq_api.h | 10 +---- drivers/common/idpf/base/idpf_lan_pf_regs.h | 7 +-- drivers/common/idpf/base/idpf_lan_txrx.h | 47 +++++++++----------- drivers/common/idpf/base/idpf_lan_vf_regs.h | 25 +++++++---- 5 files changed, 46 insertions(+), 45 deletions(-) diff --git a/drivers/common/idpf/base/idpf_controlq.c b/drivers/common/idpf/base/idpf_controlq.c index da5c930578..c24bfd23ef 100644 --- a/drivers/common/idpf/base/idpf_controlq.c +++ b/drivers/common/idpf/base/idpf_controlq.c @@ -13,7 +13,7 @@ static void idpf_ctlq_setup_regs(struct idpf_ctlq_info *cq, struct idpf_ctlq_create_info *q_create_info) { - /* set head and tail registers in our local struct */ + /* set control queue registers in our local struct */ cq->reg.head = q_create_info->reg.head; cq->reg.tail = q_create_info->reg.tail; cq->reg.len = q_create_info->reg.len; diff --git a/drivers/common/idpf/base/idpf_controlq_api.h b/drivers/common/idpf/base/idpf_controlq_api.h index 78a54f6b4c..38f5d2df3c 100644 --- a/drivers/common/idpf/base/idpf_controlq_api.h +++ b/drivers/common/idpf/base/idpf_controlq_api.h @@ -21,10 +21,7 @@ enum idpf_ctlq_type { IDPF_CTLQ_TYPE_RDMA_COMPL = 7 }; -/* - * Generic Control Queue Structures - */ - +/* Generic Control Queue Structures */ struct idpf_ctlq_reg { /* used for queue tracking */ u32 head; @@ -157,10 +154,7 @@ enum idpf_mbx_opc { idpf_mbq_opc_send_msg_to_peer_drv = 0x0804, }; -/* - * API supported for control queue management - */ - +/* API supported for control queue management */ /* Will init all required q including default mb. "q_info" is an array of * create_info structs equal to the number of control queues to be created. */ diff --git a/drivers/common/idpf/base/idpf_lan_pf_regs.h b/drivers/common/idpf/base/idpf_lan_pf_regs.h index 8542620e01..e47afad6e9 100644 --- a/drivers/common/idpf/base/idpf_lan_pf_regs.h +++ b/drivers/common/idpf/base/idpf_lan_pf_regs.h @@ -80,10 +80,11 @@ /* _ITR is ITR index, _INT is interrupt index, _itrn_indx_spacing is * spacing b/w itrn registers of the same vector. */ -#define PF_GLINT_ITR_ADDR(_ITR, _reg_start, _itrn_indx_spacing) \ - ((_reg_start) + (((_ITR)) * (_itrn_indx_spacing))) +#define PF_GLINT_ITR_ADDR(_ITR, _reg_start, _itrn_indx_spacing) \ + ((_reg_start) + ((_ITR) * (_itrn_indx_spacing))) /* For PF, itrn_indx_spacing is 4 and itrn_reg_spacing is 0x1000 */ -#define PF_GLINT_ITR(_ITR, _INT) (PF_GLINT_BASE + (((_ITR) + 1) * 4) + ((_INT) * 0x1000)) +#define PF_GLINT_ITR(_ITR, _INT) \ + (PF_GLINT_BASE + (((_ITR) + 1) * 4) + ((_INT) * 0x1000)) #define PF_GLINT_ITR_MAX_INDEX 2 #define PF_GLINT_ITR_INTERVAL_S 0 #define PF_GLINT_ITR_INTERVAL_M IDPF_M(0xFFF, PF_GLINT_ITR_INTERVAL_S) diff --git a/drivers/common/idpf/base/idpf_lan_txrx.h b/drivers/common/idpf/base/idpf_lan_txrx.h index 7b03693eb1..4951e266f0 100644 --- a/drivers/common/idpf/base/idpf_lan_txrx.h +++ b/drivers/common/idpf/base/idpf_lan_txrx.h @@ -8,9 +8,9 @@ #include "idpf_osdep.h" enum idpf_rss_hash { - /* Values 0 - 28 are reserved for future use */ - IDPF_HASH_INVALID = 0, - IDPF_HASH_NONF_UNICAST_IPV4_UDP = 29, + IDPF_HASH_INVALID = 0, + /* Values 1 - 28 are reserved for future use */ + IDPF_HASH_NONF_UNICAST_IPV4_UDP = 29, IDPF_HASH_NONF_MULTICAST_IPV4_UDP, IDPF_HASH_NONF_IPV4_UDP, IDPF_HASH_NONF_IPV4_TCP_SYN_NO_ACK, @@ -19,7 +19,7 @@ enum idpf_rss_hash { IDPF_HASH_NONF_IPV4_OTHER, IDPF_HASH_FRAG_IPV4, /* Values 37-38 are reserved */ - IDPF_HASH_NONF_UNICAST_IPV6_UDP = 39, + IDPF_HASH_NONF_UNICAST_IPV6_UDP = 39, IDPF_HASH_NONF_MULTICAST_IPV6_UDP, IDPF_HASH_NONF_IPV6_UDP, IDPF_HASH_NONF_IPV6_TCP_SYN_NO_ACK, @@ -32,34 +32,31 @@ enum idpf_rss_hash { IDPF_HASH_NONF_FCOE_RX, IDPF_HASH_NONF_FCOE_OTHER, /* Values 51-62 are reserved */ - IDPF_HASH_L2_PAYLOAD = 63, + IDPF_HASH_L2_PAYLOAD = 63, + IDPF_HASH_MAX }; /* Supported RSS offloads */ -#define IDPF_DEFAULT_RSS_HASH ( \ - BIT_ULL(IDPF_HASH_NONF_IPV4_UDP) | \ - BIT_ULL(IDPF_HASH_NONF_IPV4_SCTP) | \ - BIT_ULL(IDPF_HASH_NONF_IPV4_TCP) | \ - BIT_ULL(IDPF_HASH_NONF_IPV4_OTHER) | \ - BIT_ULL(IDPF_HASH_FRAG_IPV4) | \ - BIT_ULL(IDPF_HASH_NONF_IPV6_UDP) | \ - BIT_ULL(IDPF_HASH_NONF_IPV6_TCP) | \ - BIT_ULL(IDPF_HASH_NONF_IPV6_SCTP) | \ - BIT_ULL(IDPF_HASH_NONF_IPV6_OTHER) | \ - BIT_ULL(IDPF_HASH_FRAG_IPV6) | \ +#define IDPF_DEFAULT_RSS_HASH \ + (BIT_ULL(IDPF_HASH_NONF_IPV4_UDP) | \ + BIT_ULL(IDPF_HASH_NONF_IPV4_SCTP) | \ + BIT_ULL(IDPF_HASH_NONF_IPV4_TCP) | \ + BIT_ULL(IDPF_HASH_NONF_IPV4_OTHER) | \ + BIT_ULL(IDPF_HASH_FRAG_IPV4) | \ + BIT_ULL(IDPF_HASH_NONF_IPV6_UDP) | \ + BIT_ULL(IDPF_HASH_NONF_IPV6_TCP) | \ + BIT_ULL(IDPF_HASH_NONF_IPV6_SCTP) | \ + BIT_ULL(IDPF_HASH_NONF_IPV6_OTHER) | \ + BIT_ULL(IDPF_HASH_FRAG_IPV6) | \ BIT_ULL(IDPF_HASH_L2_PAYLOAD)) - /* TODO: Wrap below comment under internal flag - * Below 6 pcktypes are not supported by FVL or older products - * They are supported by FPK and future products - */ #define IDPF_DEFAULT_RSS_HASH_EXPANDED (IDPF_DEFAULT_RSS_HASH | \ - BIT_ULL(IDPF_HASH_NONF_IPV4_TCP_SYN_NO_ACK) | \ - BIT_ULL(IDPF_HASH_NONF_UNICAST_IPV4_UDP) | \ - BIT_ULL(IDPF_HASH_NONF_MULTICAST_IPV4_UDP) | \ - BIT_ULL(IDPF_HASH_NONF_IPV6_TCP_SYN_NO_ACK) | \ - BIT_ULL(IDPF_HASH_NONF_UNICAST_IPV6_UDP) | \ + BIT_ULL(IDPF_HASH_NONF_IPV4_TCP_SYN_NO_ACK) | \ + BIT_ULL(IDPF_HASH_NONF_UNICAST_IPV4_UDP) | \ + BIT_ULL(IDPF_HASH_NONF_MULTICAST_IPV4_UDP) | \ + BIT_ULL(IDPF_HASH_NONF_IPV6_TCP_SYN_NO_ACK) | \ + BIT_ULL(IDPF_HASH_NONF_UNICAST_IPV6_UDP) | \ BIT_ULL(IDPF_HASH_NONF_MULTICAST_IPV6_UDP)) /* For idpf_splitq_base_tx_compl_desc */ diff --git a/drivers/common/idpf/base/idpf_lan_vf_regs.h b/drivers/common/idpf/base/idpf_lan_vf_regs.h index b5ff9b2cc9..4c5249129e 100644 --- a/drivers/common/idpf/base/idpf_lan_vf_regs.h +++ b/drivers/common/idpf/base/idpf_lan_vf_regs.h @@ -94,14 +94,23 @@ * b/w itrn registers of the same vector */ #define VF_INT_ITR0(_ITR) (0x00004C00 + ((_ITR) * 4)) -#define VF_INT_ITRN_ADDR(_ITR, _reg_start, _itrn_indx_spacing) \ - ((_reg_start) + (((_ITR)) * (_itrn_indx_spacing))) -/* For VF with 16 vector support, itrn_reg_spacing is 0x4 and itrn_indx_spacing is 0x40 */ -#define VF_INT_ITRN(_INT, _ITR) (0x00002800 + ((_INT) * 4) + ((_ITR) * 0x40)) -/* For VF with 64 vector support, itrn_reg_spacing is 0x4 and itrn_indx_spacing is 0x100 */ -#define VF_INT_ITRN_64(_INT, _ITR) (0x00002C00 + ((_INT) * 4) + ((_ITR) * 0x100)) -/* For VF with 2k vector support, itrn_reg_spacing is 0x4 and itrn_indx_spacing is 0x2000 */ -#define VF_INT_ITRN_2K(_INT, _ITR) (0x00072000 + ((_INT) * 4) + ((_ITR) * 0x2000)) +#define VF_INT_ITRN_ADDR(_ITR, _reg_start, _itrn_indx_spacing) \ + ((_reg_start) + ((_ITR) * (_itrn_indx_spacing))) +/* For VF with 16 vector support, itrn_reg_spacing is 0x4, itrn_indx_spacing + * is 0x40 and base register offset is 0x00002800 + */ +#define VF_INT_ITRN(_INT, _ITR) \ + (0x00002800 + ((_INT) * 4) + ((_ITR) * 0x40)) +/* For VF with 64 vector support, itrn_reg_spacing is 0x4, itrn_indx_spacing + * is 0x100 and base register offset is 0x00002C00 + */ +#define VF_INT_ITRN_64(_INT, _ITR) \ + (0x00002C00 + ((_INT) * 4) + ((_ITR) * 0x100)) +/* For VF with 2k vector support, itrn_reg_spacing is 0x4, itrn_indx_spacing + * is 0x2000 and base register offset is 0x00072000 + */ +#define VF_INT_ITRN_2K(_INT, _ITR) \ + (0x00072000 + ((_INT) * 4) + ((_ITR) * 0x2000)) #define VF_INT_ITRN_MAX_INDEX 2 #define VF_INT_ITRN_INTERVAL_S 0 #define VF_INT_ITRN_INTERVAL_M IDPF_M(0xFFF, VF_INT_ITRN_INTERVAL_S)