From patchwork Fri Aug 11 10:00:11 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wenjing Qiao X-Patchwork-Id: 130151 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 3527A43033; Fri, 11 Aug 2023 12:04:54 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 1FE6C43251; Fri, 11 Aug 2023 12:04:54 +0200 (CEST) Received: from mgamail.intel.com (mgamail.intel.com [134.134.136.31]) by mails.dpdk.org (Postfix) with ESMTP id 60BB640E03 for ; Fri, 11 Aug 2023 12:04:52 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1691748292; x=1723284292; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=KeZBCciHkkjfGlBwvs4FTiq66XsuUbTcfYSzb/4GqRI=; b=XeYWKoMNi5ewQN+LQ/qqRYIjc5pVaSWi6AEQQdzb/NM1Mk0U7wZq3XiF oSjKUd3RiCjwHveDuCFVwB5dda9b9c1UAqfHgEZWRTF4aTCW/AxOdl/9e t4nJ5wUrCX4ni9j0dbFcPsvszq4f9/8DI3GCWN4LWnOWVQym/cqBOp2qj R3jz+efxE8FV6aG6f2WR7RKGjC66RuaY+G0eNt6Qs8GoOEwU5UbyXsh6U zspU96YDKSr6mEGnADGcUfclR9LqaqzLbLfs5CRj5H3VG5dUXwy2FhlAz D9XsSLSRfppfHvwnG5ibQCpzw8Qm3lkU9jFVPwBtrZBC81fobw/YT0fdb A==; X-IronPort-AV: E=McAfee;i="6600,9927,10798"; a="435538944" X-IronPort-AV: E=Sophos;i="6.01,165,1684825200"; d="scan'208";a="435538944" Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 Aug 2023 03:04:51 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.01,202,1684825200"; d="scan'208";a="876105371" Received: from dpdk-wenjing-02.sh.intel.com ([10.67.119.75]) by fmsmga001.fm.intel.com with ESMTP; 11 Aug 2023 03:04:53 -0700 From: Wenjing Qiao To: yuying.zhang@intel.com, beilei.xing@intel.com Cc: dev@dpdk.org, mingxia.liu@intel.com, Wenjing Qiao Subject: [PATCH v2 1/4] net/cpfl: parse flow parser file in devargs Date: Fri, 11 Aug 2023 10:00:11 +0000 Message-Id: <20230811100012.2078135-2-wenjing.qiao@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230811093032.2065099-2-wenjing.qiao@intel.com> References: <20230811093032.2065099-2-wenjing.qiao@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Add devargs "flow_parser" for rte_flow json parser. Signed-off-by: Wenjing Qiao --- Depends-on: series-29139 ("net/cpfl: support port representor") --- drivers/net/cpfl/cpfl_ethdev.c | 30 +++++++++++++++++++++++++++++- drivers/net/cpfl/cpfl_ethdev.h | 3 +++ drivers/net/cpfl/meson.build | 6 ++++++ 3 files changed, 38 insertions(+), 1 deletion(-) diff --git a/drivers/net/cpfl/cpfl_ethdev.c b/drivers/net/cpfl/cpfl_ethdev.c index 8dbc175749..a2f308fb86 100644 --- a/drivers/net/cpfl/cpfl_ethdev.c +++ b/drivers/net/cpfl/cpfl_ethdev.c @@ -21,6 +21,7 @@ #define CPFL_TX_SINGLE_Q "tx_single" #define CPFL_RX_SINGLE_Q "rx_single" #define CPFL_VPORT "vport" +#define CPFL_FLOW_PARSER "flow_parser" rte_spinlock_t cpfl_adapter_lock; /* A list for all adapters, one adapter matches one PCI device */ @@ -32,6 +33,9 @@ static const char * const cpfl_valid_args_first[] = { CPFL_TX_SINGLE_Q, CPFL_RX_SINGLE_Q, CPFL_VPORT, +#ifdef CPFL_FLOW_JSON_SUPPORT + CPFL_FLOW_PARSER, +#endif NULL }; @@ -1671,6 +1675,19 @@ parse_repr(const char *key __rte_unused, const char *value, void *args) return 0; } +#ifdef CPFL_FLOW_JSON_SUPPORT +static int +parse_parser_file(const char *key, const char *value, void *args) +{ + char *name = args; + + PMD_DRV_LOG(DEBUG, "value:\"%s\" for key:\"%s\"", value, key); + strlcpy(name, value, CPFL_FLOW_FILE_LEN); + + return 0; +} +#endif + static int cpfl_parse_devargs(struct rte_pci_device *pci_dev, struct cpfl_adapter_ext *adapter, bool first) { @@ -1719,7 +1736,18 @@ cpfl_parse_devargs(struct rte_pci_device *pci_dev, struct cpfl_adapter_ext *adap &adapter->base.is_rx_singleq); if (ret != 0) goto fail; - +#ifdef CPFL_FLOW_JSON_SUPPORT + if (rte_kvargs_get(kvlist, CPFL_FLOW_PARSER)) { + ret = rte_kvargs_process(kvlist, CPFL_FLOW_PARSER, + &parse_parser_file, cpfl_args->flow_parser); + if (ret) { + PMD_DRV_LOG(ERR, "Failed to parser flow_parser, ret: %d", ret); + goto fail; + } + } else { + cpfl_args->flow_parser[0] = '\0'; + } +#endif fail: rte_kvargs_free(kvlist); return ret; diff --git a/drivers/net/cpfl/cpfl_ethdev.h b/drivers/net/cpfl/cpfl_ethdev.h index 5bd6f930b8..cf989a29b3 100644 --- a/drivers/net/cpfl/cpfl_ethdev.h +++ b/drivers/net/cpfl/cpfl_ethdev.h @@ -87,6 +87,8 @@ #define ACC_LCE_ID 15 #define IMC_MBX_EFD_ID 0 +#define CPFL_FLOW_FILE_LEN 100 + struct cpfl_vport_param { struct cpfl_adapter_ext *adapter; uint16_t devarg_id; /* arg id from user */ @@ -100,6 +102,7 @@ struct cpfl_devargs { uint16_t req_vport_nb; uint8_t repr_args_num; struct rte_eth_devargs repr_args[CPFL_REPR_ARG_NUM_MAX]; + char flow_parser[CPFL_FLOW_FILE_LEN]; }; struct p2p_queue_chunks_info { diff --git a/drivers/net/cpfl/meson.build b/drivers/net/cpfl/meson.build index fb075c6860..0be25512c3 100644 --- a/drivers/net/cpfl/meson.build +++ b/drivers/net/cpfl/meson.build @@ -38,3 +38,9 @@ if arch_subdir == 'x86' cflags += ['-DCC_AVX512_SUPPORT'] endif endif + +js_dep = dependency('json-c', required: false, method : 'pkg-config') +if js_dep.found() + dpdk_conf.set('CPFL_FLOW_JSON_SUPPORT', true) + ext_deps += js_dep +endif \ No newline at end of file