From patchwork Fri Aug 11 08:57:49 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nithin Dabilpuram X-Patchwork-Id: 130129 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id D13D743032; Fri, 11 Aug 2023 10:59:41 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 2B61843262; Fri, 11 Aug 2023 10:58:58 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id CABB143262 for ; Fri, 11 Aug 2023 10:58:56 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 37AMkJKc002877 for ; Fri, 11 Aug 2023 01:58:56 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=gtgk2wzWhFaX7PqYEi7VD77kBnpJidsDn5+PDdiE8+I=; b=EyZrrVnua4CYAhontSAuNz5TDg25xNBkyB6RZV0dfW7LRzwcIOMvJgoY7/VQXYIWtyK9 fgjrB4u+tY23H7JYanyuvsXK3TpnhVxmBBqn2kZFTSgbny0wGK+WKjJUOMOqcbvIxlQ7 ZBKVuQP/F937yyGkBbJrkTQrbzODKnW7/wfRdTfqEfqyTrhKma8RGodnuYw2EvmQBFFv BCVw0l/RqNTkUwiogm5OxmwgPKwGHHfVDLJFXKFuhjGPpr1klPzKj5guaoASE/bVUc5S lFe+cIuqF7Mj0NJetFe+Y0thhycD3KPWaHGNyq1JRNcvhsfVPCm+mEfuxr2JUz3C1CLg xQ== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3sd8yp9r95-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Fri, 11 Aug 2023 01:58:55 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.48; Fri, 11 Aug 2023 01:58:54 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.48 via Frontend Transport; Fri, 11 Aug 2023 01:58:54 -0700 Received: from hyd1588t430.caveonetworks.com (unknown [10.29.52.204]) by maili.marvell.com (Postfix) with ESMTP id 1A53E3F706B; Fri, 11 Aug 2023 01:58:51 -0700 (PDT) From: Nithin Dabilpuram To: Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao CC: , Subject: [PATCH 15/31] common/cnxk: fix BP threshold calculation Date: Fri, 11 Aug 2023 14:27:49 +0530 Message-ID: <20230811085805.441256-15-ndabilpuram@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230811085805.441256-1-ndabilpuram@marvell.com> References: <20230811085805.441256-1-ndabilpuram@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: 5yUG4ojwWWu2G0dDygj5oiBapaOtv4q2 X-Proofpoint-GUID: 5yUG4ojwWWu2G0dDygj5oiBapaOtv4q2 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.267,Aquarius:18.0.957,Hydra:6.0.591,FMLib:17.11.176.26 definitions=2023-08-10_20,2023-08-10_01,2023-05-22_02 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Sunil Kumar Kori Current macro to calculate BP threshold were evaluating incorrect threshold because aura_limit is first shifted by shift then percentage is calculated. While first percentage should be calculated and the resultant should be shifted by shift. So formula is updated accordingly. Fixes: cb4bfd6e7bdf ("event/cnxk: support Rx adapter") Signed-off-by: Sunil Kumar Kori --- drivers/common/cnxk/roc_nix_fc.c | 2 +- drivers/common/cnxk/roc_nix_priv.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/common/cnxk/roc_nix_fc.c b/drivers/common/cnxk/roc_nix_fc.c index d58b35268e..0f9b5cbbc0 100644 --- a/drivers/common/cnxk/roc_nix_fc.c +++ b/drivers/common/cnxk/roc_nix_fc.c @@ -496,7 +496,7 @@ roc_nix_fc_npa_bp_cfg(struct roc_nix *roc_nix, uint64_t pool_id, uint8_t ena, ui aura_attr = &lf->aura_attr[aura_id]; bp_intf = 1 << nix->is_nix1; - bp_thresh = NIX_RQ_AURA_THRESH(drop_percent, aura_attr->limit >> aura_attr->shift); + bp_thresh = NIX_RQ_AURA_BP_THRESH(drop_percent, aura_attr->limit, aura_attr->shift); bpid = (aura_attr->bp_ena & 0x1) ? aura_attr->nix0_bpid : aura_attr->nix1_bpid; /* BP is already enabled. */ diff --git a/drivers/common/cnxk/roc_nix_priv.h b/drivers/common/cnxk/roc_nix_priv.h index f82e411b70..a582b9df33 100644 --- a/drivers/common/cnxk/roc_nix_priv.h +++ b/drivers/common/cnxk/roc_nix_priv.h @@ -20,7 +20,7 @@ /* Apply LBP at 75% of actual BP */ #define NIX_CQ_LPB_THRESH_FRAC (75 * 16 / 100) #define NIX_CQ_FULL_ERRATA_SKID (1024ull * 256) -#define NIX_RQ_AURA_THRESH(percent, val) (((val) * (percent)) / 100) +#define NIX_RQ_AURA_BP_THRESH(percent, limit, shift) ((((limit) * (percent)) / 100) >> (shift)) /* IRQ triggered when NIX_LF_CINTX_CNT[QCOUNT] crosses this value */ #define CQ_CQE_THRESH_DEFAULT 0x1ULL