From patchwork Fri Aug 11 08:57:45 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nithin Dabilpuram X-Patchwork-Id: 130125 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id D7F2843032; Fri, 11 Aug 2023 10:59:18 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 9FC0343264; Fri, 11 Aug 2023 10:58:45 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id 7000F4325B for ; Fri, 11 Aug 2023 10:58:44 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 37AN2WUx011282 for ; Fri, 11 Aug 2023 01:58:43 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=pqXvvDC+iMQazmEz6MuhwBCFT66XejZO6PtUNrpq4M0=; b=IFmG8TtvFIAAvMF3J5we8ScUb8j7+eqO9I/p5N9kh94JYYD734mRJR/CF16dIDmWw9Z7 GBXZnJcWgm8LG4WpDUYT1QYechiFP448W3Njhc5efzaokIPI5IrV7mSKrbKNcfzmw2av SN5KVYCUnq1V7yz8IsSGAe5CwoOwabwYdYLs1TPSimF2SkkCDmFcfWHDETmVQgiof9D3 UzHGMlwRW/s1X5FOwc6uxFRdecGcnWZcgHcjB0HgKCyTmhi6BIjz5xyKxw7xvu9YplS4 pz02OdsPKTO6lE2Plgf0fnj8dUU7z/vGwtdAUfMuF3jNGCKrM4aChS2zLoxmy5Uv+rNe hA== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3sd8ya1g94-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Fri, 11 Aug 2023 01:58:43 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.48; Fri, 11 Aug 2023 01:58:41 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.48 via Frontend Transport; Fri, 11 Aug 2023 01:58:41 -0700 Received: from hyd1588t430.caveonetworks.com (unknown [10.29.52.204]) by maili.marvell.com (Postfix) with ESMTP id 422FB3F706B; Fri, 11 Aug 2023 01:58:38 -0700 (PDT) From: Nithin Dabilpuram To: Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao CC: , , Akhil Goyal Subject: [PATCH 11/31] common/cnxk: fix different size bit operations Date: Fri, 11 Aug 2023 14:27:45 +0530 Message-ID: <20230811085805.441256-11-ndabilpuram@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230811085805.441256-1-ndabilpuram@marvell.com> References: <20230811085805.441256-1-ndabilpuram@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: 5ehsOj5gRgm73uh2M4YcOMktA8Gz4isX X-Proofpoint-GUID: 5ehsOj5gRgm73uh2M4YcOMktA8Gz4isX X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.267,Aquarius:18.0.957,Hydra:6.0.591,FMLib:17.11.176.26 definitions=2023-08-10_20,2023-08-10_01,2023-05-22_02 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Akhil Goyal Bitwise or is being done on relchan which is 32 bit, but the result is 64 bit, hence typecast to uint64_t. Fixes: 8f867a87b9c5 ("common/cnxk: enable SDP channel backpressure to TL4") Fixes: 0885429c3028 ("common/cnxk: add NIX TM hierarchy enable/disable") Signed-off-by: Akhil Goyal --- drivers/common/cnxk/roc_nix_tm_utils.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/common/cnxk/roc_nix_tm_utils.c b/drivers/common/cnxk/roc_nix_tm_utils.c index 3840d6d457..ce26ddff50 100644 --- a/drivers/common/cnxk/roc_nix_tm_utils.c +++ b/drivers/common/cnxk/roc_nix_tm_utils.c @@ -588,7 +588,7 @@ nix_tm_topology_reg_prep(struct nix *nix, struct nix_tm_node *node, reg[k] = NIX_AF_TL4X_SDP_LINK_CFG(schq); regval[k] = BIT_ULL(12); regval[k] |= BIT_ULL(13); - regval[k] |= relchan; + regval[k] |= (uint64_t)relchan; k++; } break; @@ -606,7 +606,7 @@ nix_tm_topology_reg_prep(struct nix *nix, struct nix_tm_node *node, if (!nix->sdp_link && nix->tm_link_cfg_lvl == NIX_TXSCH_LVL_TL3) { reg[k] = NIX_AF_TL3_TL2X_LINKX_CFG(schq, link); - regval[k] = BIT_ULL(12) | relchan; + regval[k] = BIT_ULL(12) | (uint64_t)relchan; k++; } @@ -625,7 +625,7 @@ nix_tm_topology_reg_prep(struct nix *nix, struct nix_tm_node *node, if (!nix->sdp_link && nix->tm_link_cfg_lvl == NIX_TXSCH_LVL_TL2) { reg[k] = NIX_AF_TL3_TL2X_LINKX_CFG(schq, link); - regval[k] = BIT_ULL(12) | relchan; + regval[k] = BIT_ULL(12) | (uint64_t)relchan; k++; }