@@ -6625,3 +6625,9 @@ RTE_PMD_REGISTER_PARAM_STRING(net_hns3,
HNS3_DEVARG_MBX_TIME_LIMIT_MS "=<uint16> ");
RTE_LOG_REGISTER_SUFFIX(hns3_logtype_init, init, NOTICE);
RTE_LOG_REGISTER_SUFFIX(hns3_logtype_driver, driver, NOTICE);
+#ifdef RTE_ETHDEV_DEBUG_RX
+RTE_LOG_REGISTER_SUFFIX(hns3_logtype_rx, rx, DEBUG);
+#endif
+#ifdef RTE_ETHDEV_DEBUG_TX
+RTE_LOG_REGISTER_SUFFIX(hns3_logtype_tx, tx, DEBUG);
+#endif
@@ -31,4 +31,22 @@ extern int hns3_logtype_driver;
#define hns3_dbg(hw, fmt, args...) \
PMD_DRV_LOG_RAW(hw, RTE_LOG_DEBUG, fmt "\n", ## args)
+#ifdef RTE_ETHDEV_DEBUG_RX
+extern int hns3_logtype_rx;
+#define PMD_RX_LOG(hw, level, fmt, args...) \
+ rte_log(RTE_LOG_ ## level, hns3_logtype_rx, "%s %s(): " fmt "\n", \
+ (hw)->data->name, __func__, ## args)
+#else
+#define PMD_RX_LOG(hw, level, fmt, args...) do { } while (0)
+#endif
+
+#ifdef RTE_ETHDEV_DEBUG_TX
+extern int hns3_logtype_tx;
+#define PMD_TX_LOG(hw, level, fmt, args...) \
+ rte_log(RTE_LOG_ ## level, hns3_logtype_tx, "%s %s(): " fmt "\n", \
+ (hw)->data->name, __func__, ## args)
+#else
+#define PMD_TX_LOG(hw, level, fmt, args...) do { } while (0)
+#endif
+
#endif /* HNS3_LOGS_H */
@@ -2618,6 +2618,7 @@ hns3_recv_scattered_pkts(void *rx_queue,
*/
rxd = rxdp[(bd_base_info & (1u << HNS3_RXD_VLD_B)) -
(1u << HNS3_RXD_VLD_B)];
+ RX_BD_LOG(&rxq->hns->hw, DEBUG, &rxd);
nmb = hns3_rx_alloc_buffer(rxq);
if (unlikely(nmb == NULL)) {
@@ -4274,6 +4275,8 @@ hns3_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
tx_next_use = 0;
tx_bak_pkt = txq->sw_ring;
}
+ if (m_seg != NULL)
+ TX_BD_LOG(&txq->hns->hw, DEBUG, desc);
i++;
} while (m_seg != NULL);
@@ -4281,6 +4284,7 @@ hns3_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
/* Add end flag for the last Tx Buffer Descriptor */
desc->tx.tp_fe_sc_vld_ra_ri |=
rte_cpu_to_le_16(BIT(HNS3_TXD_FE_B));
+ TX_BD_LOG(&txq->hns->hw, DEBUG, desc);
/* Increment bytes counter */
txq->basic_stats.bytes += tx_pkt->pkt_len;
@@ -553,6 +553,35 @@ struct hns3_tx_queue {
bool enabled; /* indicate if Tx queue has been enabled */
};
+#define RX_BD_LOG(hw, level, rxdp) \
+ PMD_RX_LOG(hw, level, "Rx descriptor: " \
+ "l234_info=%#x pkt_len=%u size=%u rss_hash=%#x fd_id=%u vlan_tag=%u " \
+ "o_dm_vlan_id_fb=%#x ot_vlan_tag=%u bd_base_info=%#x", \
+ rte_le_to_cpu_32((rxdp)->rx.l234_info), \
+ rte_le_to_cpu_16((rxdp)->rx.pkt_len), \
+ rte_le_to_cpu_16((rxdp)->rx.size), \
+ rte_le_to_cpu_32((rxdp)->rx.rss_hash), \
+ rte_le_to_cpu_16((rxdp)->rx.fd_id), \
+ rte_le_to_cpu_16((rxdp)->rx.vlan_tag), \
+ rte_le_to_cpu_16((rxdp)->rx.o_dm_vlan_id_fb), \
+ rte_le_to_cpu_16((rxdp)->rx.ot_vlan_tag), \
+ rte_le_to_cpu_32((rxdp)->rx.bd_base_info))
+
+#define TX_BD_LOG(hw, level, txdp) \
+ PMD_TX_LOG(hw, level, "Tx descriptor: " \
+ "vlan_tag=%u send_size=%u type_cs_vlan_tso_len=%#x outer_vlan_tag=%u " \
+ "tv=%#x ol_type_vlan_len_msec=%#x paylen_fd_dop_ol4cs=%#x " \
+ "tp_fe_sc_vld_ra_ri=%#x ckst_mss=%u", \
+ rte_le_to_cpu_16((txdp)->tx.vlan_tag), \
+ rte_le_to_cpu_16((txdp)->tx.send_size), \
+ rte_le_to_cpu_32((txdp)->tx.type_cs_vlan_tso_len), \
+ rte_le_to_cpu_16((txdp)->tx.outer_vlan_tag), \
+ rte_le_to_cpu_16((txdp)->tx.tv), \
+ rte_le_to_cpu_32((txdp)->tx.ol_type_vlan_len_msec), \
+ rte_le_to_cpu_32((txdp)->tx.paylen_fd_dop_ol4cs), \
+ rte_le_to_cpu_16((txdp)->tx.tp_fe_sc_vld_ra_ri), \
+ rte_le_to_cpu_16((txdp)->tx.ckst_mss))
+
#define HNS3_GET_TX_QUEUE_PEND_BD_NUM(txq) \
((txq)->nb_tx_desc - 1 - (txq)->tx_bd_ready)