From patchwork Thu May 18 15:16:23 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qiming Yang X-Patchwork-Id: 126999 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 7C62E42AF1; Thu, 18 May 2023 17:35:01 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id A8BE142D47; Thu, 18 May 2023 17:34:30 +0200 (CEST) Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by mails.dpdk.org (Postfix) with ESMTP id 5268C42D2D for ; Thu, 18 May 2023 17:34:28 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1684424068; x=1715960068; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=IO5PT5CPJ9BSU4hdc+3VVIb1DZdKE2cky/DBcLtln7Y=; b=l5wG8TfkqBVpdfGJ2+8BLiKBPZprQTqMfeG1ielsFfkcSCL58lvmuuxK AGA+10DOiZiFg6po1j7SuXAc9FZsKwO37rPHQNCUMM3fHGTpvNcANuY0C 46WmLbV4nTcqFdK8Rihcp8A4VmPedT23nlgX4ol6QvwdZ8l5ylZcEfcnd HRRyJiyg+IqCreOHHUrXqCv7NzmmzIqpn+94ruzGEdMrg/W5Ty/e4onYt rHS3ZIIVuMbZJ5d8FaV6LMbWhkgh/q6wusF7JLfct1tTl41FzgRgi56uk JwwtdIvDmzRjpri/GRqvwjeOg8WOJsEYTLu0N2MAvXMkat7H7H1JalRyd Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10714"; a="341527655" X-IronPort-AV: E=Sophos;i="5.99,285,1677571200"; d="scan'208";a="341527655" Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 May 2023 08:34:27 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10714"; a="705235070" X-IronPort-AV: E=Sophos;i="5.99,285,1677571200"; d="scan'208";a="705235070" Received: from dpdk-qiming3.sh.intel.com ([10.67.111.4]) by fmsmga007.fm.intel.com with ESMTP; 18 May 2023 08:34:26 -0700 From: Qiming Yang To: dev@dpdk.org Cc: qi.z.zhang@intel.com, Qiming Yang , Wojciech Drewek Subject: [PATCH v2 05/20] net/ice/base: introduce a non-atomic function Date: Thu, 18 May 2023 15:16:23 +0000 Message-Id: <20230518151638.1207021-6-qiming.yang@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230518151638.1207021-1-qiming.yang@intel.com> References: <20230427062001.478032-1-qiming.yang@intel.com> <20230518151638.1207021-1-qiming.yang@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org recipe_bitmap is not aligned to 8 bytes in ice_aqc_recipe_data_elem structure and set_bit is a atomic operation we end up with a split lock. The reason for this is that recipe_bitmap might end up being in two cache lines because it's not aligned. Fix this by introducing non-atomic function ice_set_recipe_index to replace ice_set_bit in this specific case. Signed-off-by: Wojciech Drewek Signed-off-by: Qiming Yang --- drivers/net/ice/base/ice_bitops.h | 7 +++++++ drivers/net/ice/base/ice_switch.c | 19 +++++++++++++++---- 2 files changed, 22 insertions(+), 4 deletions(-) diff --git a/drivers/net/ice/base/ice_bitops.h b/drivers/net/ice/base/ice_bitops.h index 5384e99415..df00c859ac 100644 --- a/drivers/net/ice/base/ice_bitops.h +++ b/drivers/net/ice/base/ice_bitops.h @@ -11,6 +11,13 @@ /* Define the size of the bitmap chunk */ typedef u32 ice_bitmap_t; +/* NOTE! + * Do not use any of the functions declared in this file + * on memory that was not declared with ice_declare_bitmap. + * Not following this rule might cause issues like split + * locks. + */ + /* Number of bits per bitmap chunk */ #define BITS_PER_CHUNK (BITS_PER_BYTE * sizeof(ice_bitmap_t)) /* Determine which chunk a bit belongs in */ diff --git a/drivers/net/ice/base/ice_switch.c b/drivers/net/ice/base/ice_switch.c index cd6237136e..c71861a36d 100644 --- a/drivers/net/ice/base/ice_switch.c +++ b/drivers/net/ice/base/ice_switch.c @@ -7163,6 +7163,17 @@ ice_find_free_recp_res_idx(struct ice_hw *hw, const ice_bitmap_t *profiles, return (u16)ice_bitmap_hweight(free_idx, ICE_MAX_FV_WORDS); } +static void ice_set_recipe_index(unsigned long idx, u8 *bitmap) +{ + u32 byte = idx / BITS_PER_BYTE; + u32 bit = idx % BITS_PER_BYTE; + + if (byte >= 8) + return; + + bitmap[byte] |= 1 << bit; +} + /** * ice_add_sw_recipe - function to call AQ calls to create switch recipe * @hw: pointer to hardware structure @@ -7290,10 +7301,10 @@ ice_add_sw_recipe(struct ice_hw *hw, struct ice_sw_recipe *rm, } /* fill recipe dependencies */ - ice_zero_bitmap((ice_bitmap_t *)buf[recps].recipe_bitmap, - ICE_MAX_NUM_RECIPES); - ice_set_bit(buf[recps].recipe_indx, - (ice_bitmap_t *)buf[recps].recipe_bitmap); + ice_memset(buf[recps].recipe_bitmap, 0, + sizeof(buf[recps].recipe_bitmap), ICE_NONDMA_MEM); + ice_set_recipe_index(buf[recps].recipe_indx, + buf[recps].recipe_bitmap); buf[recps].content.act_ctrl_fwd_priority = rm->priority; recps++; }