From patchwork Thu May 18 15:16:36 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qiming Yang X-Patchwork-Id: 127012 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 7765342AF1; Thu, 18 May 2023 17:36:34 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id A280342DB9; Thu, 18 May 2023 17:34:49 +0200 (CEST) Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by mails.dpdk.org (Postfix) with ESMTP id 4DE5D42DAD for ; Thu, 18 May 2023 17:34:47 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1684424088; x=1715960088; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=HghU0ET1o7wgN6VtGDNkwkZAz19S08X2oOFz4NSDY5w=; b=Ndqz5ef3ip5VABfUmoCTjQKuAOGSwSg72RsOPdx2yze+mEnJH+n+BH1/ CgxUaPck/z4Il2ahBU5PGPsu7mADNVFZjOSzQ60cuOVTbhY2FNIMtAXii NTFghqMNH9d2zuLEr+3coZsZFWrkNdwf6B5IoC/E2Ko/VzFUR0EACt9Za 2KrTzw3OusKJ5NhCEcbbtGseXNWML/iCPnHZML2YEs2tHiOoOMI5DTBGs H5DtgoCwuyUqx5/2b+SMXN/SlTGKkxkz0+4IODIbHRoYjZ/Hlncgxuhlv 0m6FSLiMbzrmDcYzCcL6Txm7JGRUOJBsjTRPvyif+fYjRia3ke3R/4qSu w==; X-IronPort-AV: E=McAfee;i="6600,9927,10714"; a="341527799" X-IronPort-AV: E=Sophos;i="5.99,285,1677571200"; d="scan'208";a="341527799" Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 May 2023 08:34:46 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10714"; a="705235257" X-IronPort-AV: E=Sophos;i="5.99,285,1677571200"; d="scan'208";a="705235257" Received: from dpdk-qiming3.sh.intel.com ([10.67.111.4]) by fmsmga007.fm.intel.com with ESMTP; 18 May 2023 08:34:45 -0700 From: Qiming Yang To: dev@dpdk.org Cc: qi.z.zhang@intel.com, Qiming Yang , Vignesh Sridhar Subject: [PATCH v2 18/20] net/ice/base: fix static analyzer bug Date: Thu, 18 May 2023 15:16:36 +0000 Message-Id: <20230518151638.1207021-19-qiming.yang@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230518151638.1207021-1-qiming.yang@intel.com> References: <20230427062001.478032-1-qiming.yang@intel.com> <20230518151638.1207021-1-qiming.yang@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org The default condition in the switch statement in ice_sched_get_psm_clk_freq() is an unreachable code. The variable clk_src is restricted to values 0 to 3 with the bit mask and shift values set. Fixes: 76ac9d771c97 ("net/ice/base: read PSM clock frequency from register") Signed-off-by: Vignesh Sridhar Signed-off-by: Qiming Yang --- drivers/net/ice/base/ice_sched.c | 16 ++++++---------- drivers/net/ice/base/ice_sched.h | 5 +++++ 2 files changed, 11 insertions(+), 10 deletions(-) diff --git a/drivers/net/ice/base/ice_sched.c b/drivers/net/ice/base/ice_sched.c index 83cd152388..f558eccb93 100644 --- a/drivers/net/ice/base/ice_sched.c +++ b/drivers/net/ice/base/ice_sched.c @@ -1417,11 +1417,6 @@ void ice_sched_get_psm_clk_freq(struct ice_hw *hw) clk_src = (val & GLGEN_CLKSTAT_SRC_PSM_CLK_SRC_M) >> GLGEN_CLKSTAT_SRC_PSM_CLK_SRC_S; -#define PSM_CLK_SRC_367_MHZ 0x0 -#define PSM_CLK_SRC_416_MHZ 0x1 -#define PSM_CLK_SRC_446_MHZ 0x2 -#define PSM_CLK_SRC_390_MHZ 0x3 - switch (clk_src) { case PSM_CLK_SRC_367_MHZ: hw->psm_clk_freq = ICE_PSM_CLK_367MHZ_IN_HZ; @@ -1435,11 +1430,12 @@ void ice_sched_get_psm_clk_freq(struct ice_hw *hw) case PSM_CLK_SRC_390_MHZ: hw->psm_clk_freq = ICE_PSM_CLK_390MHZ_IN_HZ; break; - default: - ice_debug(hw, ICE_DBG_SCHED, "PSM clk_src unexpected %u\n", - clk_src); - /* fall back to a safe default */ - hw->psm_clk_freq = ICE_PSM_CLK_446MHZ_IN_HZ; + + /* default condition is not required as clk_src is restricted + * to a 2-bit value from GLGEN_CLKSTAT_SRC_PSM_CLK_SRC_M mask. + * The above switch statements cover the possible values of + * this variable. + */ } } diff --git a/drivers/net/ice/base/ice_sched.h b/drivers/net/ice/base/ice_sched.h index a71619ebf0..c54f5ca9a0 100644 --- a/drivers/net/ice/base/ice_sched.h +++ b/drivers/net/ice/base/ice_sched.h @@ -38,6 +38,11 @@ #define ICE_PSM_CLK_446MHZ_IN_HZ 446428571 #define ICE_PSM_CLK_390MHZ_IN_HZ 390625000 +#define PSM_CLK_SRC_367_MHZ 0x0 +#define PSM_CLK_SRC_416_MHZ 0x1 +#define PSM_CLK_SRC_446_MHZ 0x2 +#define PSM_CLK_SRC_390_MHZ 0x3 + struct rl_profile_params { u32 bw; /* in Kbps */ u16 rl_multiplier;