From patchwork Thu May 18 15:16:28 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qiming Yang X-Patchwork-Id: 127004 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id DA42042AF1; Thu, 18 May 2023 17:35:45 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 2C7CD42D73; Thu, 18 May 2023 17:34:37 +0200 (CEST) Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by mails.dpdk.org (Postfix) with ESMTP id E3ACF42D65 for ; Thu, 18 May 2023 17:34:35 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1684424076; x=1715960076; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=lb333tuOyBEOQbOnkVopabBBEkYV2Wf9LkCqHnXVZ3E=; b=ihuk8J4F6JvsQq0nhckteDMoAADdGF8M/rV7t9i/cCe7k0SO5t06BjcA NveVdHrQoaM2QUnF6J0INKtGTpsY05ZokAXWmlPjO2l3C8+u2J4ndzDlK 7+EASfB4mnjbW+FPOzSO00UdhfYSi0XeMWOonNNG7SXDbWOAaF5+1Aegy ynWCL8lae0o7ObO8FY8qc/2KKYKGbBn+u20FwJlrRhW3o14layTNgy6KZ yr2FrISZHrMDDMlRyY9muH98emFC8WjBYadJelcSTjoIheXlC727QXEZ1 UvoO19hjMG1GrzDyfI+PX0VS3wWqFrMxEfqAUHRbsbDEaoexOrQdw5Nc3 A==; X-IronPort-AV: E=McAfee;i="6600,9927,10714"; a="341527700" X-IronPort-AV: E=Sophos;i="5.99,285,1677571200"; d="scan'208";a="341527700" Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 May 2023 08:34:35 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10714"; a="705235127" X-IronPort-AV: E=Sophos;i="5.99,285,1677571200"; d="scan'208";a="705235127" Received: from dpdk-qiming3.sh.intel.com ([10.67.111.4]) by fmsmga007.fm.intel.com with ESMTP; 18 May 2023 08:34:34 -0700 From: Qiming Yang To: dev@dpdk.org Cc: qi.z.zhang@intel.com, Qiming Yang , Jacob Keller Subject: [PATCH v2 10/20] net/ice/base: reduce time to read Option data Date: Thu, 18 May 2023 15:16:28 +0000 Message-Id: <20230518151638.1207021-11-qiming.yang@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230518151638.1207021-1-qiming.yang@intel.com> References: <20230427062001.478032-1-qiming.yang@intel.com> <20230518151638.1207021-1-qiming.yang@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Re-write ice_get_orom_civd_data to allocate memory to store the Option ROM data. This change significantly reduces the time to read the Option ROM CIVD section from ~10 seconds down to ~1 second. Signed-off-by: Jacob Keller Signed-off-by: Qiming Yang --- drivers/net/ice/base/ice_nvm.c | 50 +++++++++++++++++++++++++--------- 1 file changed, 37 insertions(+), 13 deletions(-) diff --git a/drivers/net/ice/base/ice_nvm.c b/drivers/net/ice/base/ice_nvm.c index cb45cb8134..e46aded12a 100644 --- a/drivers/net/ice/base/ice_nvm.c +++ b/drivers/net/ice/base/ice_nvm.c @@ -724,43 +724,67 @@ static enum ice_status ice_get_orom_civd_data(struct ice_hw *hw, enum ice_bank_select bank, struct ice_orom_civd_info *civd) { - struct ice_orom_civd_info tmp; + u8 *orom_data; + enum ice_status status; u32 offset; /* The CIVD section is located in the Option ROM aligned to 512 bytes. * The first 4 bytes must contain the ASCII characters "$CIV". * A simple modulo 256 sum of all of the bytes of the structure must * equal 0. + * + * The exact location is unknown and varies between images but is + * usually somewhere in the middle of the bank. We need to scan the + * Option ROM bank to locate it. + * + * It's significantly faster to read the entire Option ROM up front + * using the maximum page size, than to read each possible location + * with a separate firmware command. */ + orom_data = (u8 *)ice_calloc(hw, hw->flash.banks.orom_size, sizeof(u8)); + if (!orom_data) + return ICE_ERR_NO_MEMORY; + + status = ice_read_flash_module(hw, bank, ICE_SR_1ST_OROM_BANK_PTR, 0, + orom_data, hw->flash.banks.orom_size); + if (status) { + ice_debug(hw, ICE_DBG_NVM, "Unable to read Option ROM data\n"); + return status; + } + + /* Scan the memory buffer to locate the CIVD data section */ for (offset = 0; (offset + 512) <= hw->flash.banks.orom_size; offset += 512) { - enum ice_status status; + struct ice_orom_civd_info *tmp; u8 sum = 0, i; - status = ice_read_flash_module(hw, bank, ICE_SR_1ST_OROM_BANK_PTR, - offset, (u8 *)&tmp, sizeof(tmp)); - if (status) { - ice_debug(hw, ICE_DBG_NVM, "Unable to read Option ROM CIVD data\n"); - return status; - } + tmp = (struct ice_orom_civd_info *)&orom_data[offset]; /* Skip forward until we find a matching signature */ - if (memcmp("$CIV", tmp.signature, sizeof(tmp.signature)) != 0) + if (memcmp("$CIV", tmp->signature, sizeof(tmp->signature)) != 0) continue; + ice_debug(hw, ICE_DBG_NVM, "Found CIVD section at offset %u\n", + offset); + /* Verify that the simple checksum is zero */ - for (i = 0; i < sizeof(tmp); i++) - sum += ((u8 *)&tmp)[i]; + for (i = 0; i < sizeof(*tmp); i++) + sum += ((u8 *)tmp)[i]; if (sum) { ice_debug(hw, ICE_DBG_NVM, "Found CIVD data with invalid checksum of %u\n", sum); - return ICE_ERR_NVM; + goto err_invalid_checksum; } - *civd = tmp; + *civd = *tmp; + ice_free(hw, orom_data); return ICE_SUCCESS; } + ice_debug(hw, ICE_DBG_NVM, "Unable to locate CIVD data within the Option ROM\n"); + +err_invalid_checksum: + ice_free(hw, orom_data); return ICE_ERR_NVM; }