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dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.161 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.161; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.161) by CY4PEPF0000E9D0.mail.protection.outlook.com (10.167.241.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6363.21 via Frontend Transport; Wed, 3 May 2023 11:50:38 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.67) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.5; Wed, 3 May 2023 04:50:25 -0700 Received: from nvidia.com (10.126.231.37) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.37; Wed, 3 May 2023 04:50:21 -0700 From: Tal Shnaiderman To: CC: , , , , , Subject: [PATCH 1/3] net/mlx5: support multi-packet RQ on Windows Date: Wed, 3 May 2023 14:49:19 +0300 Message-ID: <20230503114921.4588-2-talshn@nvidia.com> X-Mailer: git-send-email 2.16.1.windows.4 In-Reply-To: <20230503114921.4588-1-talshn@nvidia.com> References: <20230503114921.4588-1-talshn@nvidia.com> MIME-Version: 1.0 X-Originating-IP: [10.126.231.37] X-ClientProxiedBy: rnnvmail201.nvidia.com (10.129.68.8) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000E9D0:EE_|SJ2PR12MB7963:EE_ X-MS-Office365-Filtering-Correlation-Id: 199269b2-2c18-430e-c8ee-08db4bcc9d01 X-LD-Processed: 43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 03 May 2023 11:50:38.1514 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 199269b2-2c18-430e-c8ee-08db4bcc9d01 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000E9D0.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ2PR12MB7963 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Multi-Packet RQ can further save PCIe bandwidth by posting a single large buffer for multiple packets. Instead of posting a buffer per a packet, one large buffer is posted to receive multiple packets on the buffer. Add support for multi-packet RQ on Windows. The feature is disabled by default and can by enabled by setting mprq_en=1 in the PMD specific arguments. Signed-off-by: Tal Shnaiderman Tested-by: Pier Damouny --- drivers/common/mlx5/mlx5_devx_cmds.c | 3 +++ drivers/common/mlx5/mlx5_devx_cmds.h | 2 ++ drivers/common/mlx5/windows/mlx5_win_defs.h | 8 +++++++- drivers/net/mlx5/windows/mlx5_os.c | 26 ++++++++++++++++++++++++++ 4 files changed, 38 insertions(+), 1 deletion(-) diff --git a/drivers/common/mlx5/mlx5_devx_cmds.c b/drivers/common/mlx5/mlx5_devx_cmds.c index d0907fcd49..096bd1d520 100644 --- a/drivers/common/mlx5/mlx5_devx_cmds.c +++ b/drivers/common/mlx5/mlx5_devx_cmds.c @@ -1076,6 +1076,9 @@ mlx5_devx_cmd_query_hca_attr(void *ctx, general_obj_types) & MLX5_GENERAL_OBJ_TYPES_CAP_CONN_TRACK_OFFLOAD); attr->rq_delay_drop = MLX5_GET(cmd_hca_cap, hcattr, rq_delay_drop); + attr->striding_rq = MLX5_GET(cmd_hca_cap, hcattr, striding_rq); + attr->ext_stride_num_range = + MLX5_GET(cmd_hca_cap, hcattr, ext_stride_num_range); attr->max_flow_counter_15_0 = MLX5_GET(cmd_hca_cap, hcattr, max_flow_counter_15_0); attr->max_flow_counter_31_16 = MLX5_GET(cmd_hca_cap, hcattr, diff --git a/drivers/common/mlx5/mlx5_devx_cmds.h b/drivers/common/mlx5/mlx5_devx_cmds.h index ce173bc36a..9e7992b1c6 100644 --- a/drivers/common/mlx5/mlx5_devx_cmds.h +++ b/drivers/common/mlx5/mlx5_devx_cmds.h @@ -282,6 +282,8 @@ struct mlx5_hca_attr { uint32_t crypto_wrapped_import_method:1; uint16_t esw_mgr_vport_id; /* E-Switch Mgr vport ID . */ uint16_t max_wqe_sz_sq; + uint32_t striding_rq:1; + uint32_t ext_stride_num_range:1; uint32_t set_reg_c:8; uint32_t nic_flow_table:1; uint32_t modify_outer_ip_ecn:1; diff --git a/drivers/common/mlx5/windows/mlx5_win_defs.h b/drivers/common/mlx5/windows/mlx5_win_defs.h index 65da820c5e..885114655f 100644 --- a/drivers/common/mlx5/windows/mlx5_win_defs.h +++ b/drivers/common/mlx5/windows/mlx5_win_defs.h @@ -270,4 +270,10 @@ enum { MLX5_MATCH_INNER_HEADERS = RTE_BIT32(2), }; -#endif /* MLX5_WIN_DEFS_H */ +#define MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES 9 +#define MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES 16 +#define MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES 6 +#define MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES 13 +#define MLX5_EXT_MIN_SINGLE_WQE_LOG_NUM_STRIDES 3 +#define IB_QPT_RAW_PACKET 8 +#endif /* __MLX5_WIN_DEFS_H__ */ diff --git a/drivers/net/mlx5/windows/mlx5_os.c b/drivers/net/mlx5/windows/mlx5_os.c index f401264b61..0caa8931e4 100644 --- a/drivers/net/mlx5/windows/mlx5_os.c +++ b/drivers/net/mlx5/windows/mlx5_os.c @@ -187,6 +187,32 @@ mlx5_os_capabilities_prepare(struct mlx5_dev_ctx_shared *sh) if (sh->dev_cap.tso) sh->dev_cap.tso_max_payload_sz = 1 << hca_attr->max_lso_cap; DRV_LOG(DEBUG, "Counters are not supported."); + if (hca_attr->striding_rq) { + sh->dev_cap.mprq.enabled = 1; + sh->dev_cap.mprq.log_min_stride_size = + MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES; + sh->dev_cap.mprq.log_max_stride_size = + MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES; + if (hca_attr->ext_stride_num_range) + sh->dev_cap.mprq.log_min_stride_num = + MLX5_EXT_MIN_SINGLE_WQE_LOG_NUM_STRIDES; + else + sh->dev_cap.mprq.log_min_stride_num = + MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES; + sh->dev_cap.mprq.log_max_stride_num = + MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES; + DRV_LOG(DEBUG, "\tmin_single_stride_log_num_of_bytes: %u", + sh->dev_cap.mprq.log_min_stride_size); + DRV_LOG(DEBUG, "\tmax_single_stride_log_num_of_bytes: %u", + sh->dev_cap.mprq.log_max_stride_size); + DRV_LOG(DEBUG, "\tmin_single_wqe_log_num_of_strides: %u", + sh->dev_cap.mprq.log_min_stride_num); + DRV_LOG(DEBUG, "\tmax_single_wqe_log_num_of_strides: %u", + sh->dev_cap.mprq.log_max_stride_num); + DRV_LOG(DEBUG, "\tmin_stride_wqe_log_size: %u", + sh->dev_cap.mprq.log_min_stride_wqe_size); + DRV_LOG(DEBUG, "Device supports Multi-Packet RQ."); + } if (hca_attr->rss_ind_tbl_cap) { /* * DPDK doesn't support larger/variable indirection tables.