diff --git a/drivers/common/idpf/base/virtchnl.h b/drivers/common/idpf/base/virtchnl.h
index 3008802c4a..54d66c4913 100644
--- a/drivers/common/idpf/base/virtchnl.h
+++ b/drivers/common/idpf/base/virtchnl.h
@@ -184,6 +184,19 @@ enum virtchnl_ops {
 	VIRTCHNL_OP_CONFIG_QUANTA = 113,
 	VIRTCHNL_OP_FLOW_SUBSCRIBE = 114,
 	VIRTCHNL_OP_FLOW_UNSUBSCRIBE = 115,
+	VIRTCHNL_OP_SYNCE_GET_PHY_REC_CLK_OUT = 116,
+	VIRTCHNL_OP_SYNCE_SET_PHY_REC_CLK_OUT = 117,
+	VIRTCHNL_OP_SYNCE_GET_CGU_REF_PRIO = 118,
+	VIRTCHNL_OP_SYNCE_SET_CGU_REF_PRIO = 119,
+	VIRTCHNL_OP_SYNCE_GET_INPUT_PIN_CFG = 120,
+	VIRTCHNL_OP_SYNCE_SET_INPUT_PIN_CFG = 121,
+	VIRTCHNL_OP_SYNCE_GET_OUTPUT_PIN_CFG = 122,
+	VIRTCHNL_OP_SYNCE_SET_OUTPUT_PIN_CFG = 123,
+	VIRTCHNL_OP_SYNCE_GET_CGU_ABILITIES = 124,
+	VIRTCHNL_OP_SYNCE_GET_CGU_DPLL_STATUS = 125,
+	VIRTCHNL_OP_SYNCE_SET_CGU_DPLL_CONFIG = 126,
+	VIRTCHNL_OP_SYNCE_GET_CGU_INFO = 127,
+	VIRTCHNL_OP_SYNCE_GET_HW_INFO = 128,
 	VIRTCHNL_OP_MAX,
 };
 
@@ -294,6 +307,32 @@ static inline const char *virtchnl_op_str(enum virtchnl_ops v_opcode)
 		return "VIRTCHNL_OP_1588_PTP_SET_PIN_CFG";
 	case VIRTCHNL_OP_1588_PTP_EXT_TIMESTAMP:
 		return "VIRTCHNL_OP_1588_PTP_EXT_TIMESTAMP";
+	case VIRTCHNL_OP_SYNCE_GET_PHY_REC_CLK_OUT:
+		return "VIRTCHNL_OP_SYNCE_GET_PHY_REC_CLK_OUT";
+	case VIRTCHNL_OP_SYNCE_SET_PHY_REC_CLK_OUT:
+		return "VIRTCHNL_OP_SYNCE_SET_PHY_REC_CLK_OUT";
+	case VIRTCHNL_OP_SYNCE_GET_CGU_REF_PRIO:
+		return "VIRTCHNL_OP_SYNCE_GET_CGU_REF_PRIO";
+	case VIRTCHNL_OP_SYNCE_SET_CGU_REF_PRIO:
+		return "VIRTCHNL_OP_SYNCE_SET_CGU_REF_PRIO";
+	case VIRTCHNL_OP_SYNCE_GET_INPUT_PIN_CFG:
+		return "VIRTCHNL_OP_SYNCE_GET_INPUT_PIN_CFG";
+	case VIRTCHNL_OP_SYNCE_SET_INPUT_PIN_CFG:
+		return "VIRTCHNL_OP_SYNCE_SET_INPUT_PIN_CFG";
+	case VIRTCHNL_OP_SYNCE_GET_OUTPUT_PIN_CFG:
+		return "VIRTCHNL_OP_SYNCE_GET_OUTPUT_PIN_CFG";
+	case VIRTCHNL_OP_SYNCE_SET_OUTPUT_PIN_CFG:
+		return "VIRTCHNL_OP_SYNCE_SET_OUTPUT_PIN_CFG";
+	case VIRTCHNL_OP_SYNCE_GET_CGU_ABILITIES:
+		return "VIRTCHNL_OP_SYNCE_GET_CGU_ABILITIES";
+	case VIRTCHNL_OP_SYNCE_GET_CGU_DPLL_STATUS:
+		return "VIRTCHNL_OP_SYNCE_GET_CGU_DPLL_STATUS";
+	case VIRTCHNL_OP_SYNCE_SET_CGU_DPLL_CONFIG:
+		return "VIRTCHNL_OP_SYNCE_SET_CGU_DPLL_CONFIG";
+	case VIRTCHNL_OP_SYNCE_GET_CGU_INFO:
+		return "VIRTCHNL_OP_SYNCE_GET_CGU_INFO";
+	case VIRTCHNL_OP_SYNCE_GET_HW_INFO:
+		return "VIRTCHNL_OP_SYNCE_GET_HW_INFO";
 	case VIRTCHNL_OP_ENABLE_QUEUES_V2:
 		return "VIRTCHNL_OP_ENABLE_QUEUES_V2";
 	case VIRTCHNL_OP_DISABLE_QUEUES_V2:
@@ -2065,6 +2104,19 @@ VIRTCHNL_CHECK_STRUCT_LEN(12, virtchnl_quanta_cfg);
  *   VIRTCHNL_OP_1588_PTP_GET_PIN_CFGS
  *   VIRTCHNL_OP_1588_PTP_SET_PIN_CFG
  *   VIRTCHNL_OP_1588_PTP_EXT_TIMESTAMP
+ *   VIRTCHNL_OP_SYNCE_GET_PHY_REC_CLK_OUT
+ *   VIRTCHNL_OP_SYNCE_SET_PHY_REC_CLK_OUT
+ *   VIRTCHNL_OP_SYNCE_GET_CGU_REF_PRIO
+ *   VIRTCHNL_OP_SYNCE_SET_CGU_REF_PRIO
+ *   VIRTCHNL_OP_SYNCE_GET_INPUT_PIN_CFG
+ *   VIRTCHNL_OP_SYNCE_SET_INPUT_PIN_CFG
+ *   VIRTCHNL_OP_SYNCE_GET_OUTPUT_PIN_CFG
+ *   VIRTCHNL_OP_SYNCE_SET_OUTPUT_PIN_CFG
+ *   VIRTCHNL_OP_SYNCE_GET_CGU_ABILITIES
+ *   VIRTCHNL_OP_SYNCE_GET_CGU_DPLL_STATUS
+ *   VIRTCHNL_OP_SYNCE_SET_CGU_DPLL_CONFIG
+ *   VIRTCHNL_OP_SYNCE_GET_CGU_INFO
+ *   VIRTCHNL_OP_SYNCE_GET_HW_INFO
  *
  * Support for offloading control of the device PTP hardware clock (PHC) is enabled
  * by VIRTCHNL_VF_CAP_PTP. This capability allows a VF to request that PF
@@ -2085,6 +2137,7 @@ VIRTCHNL_CHECK_STRUCT_LEN(12, virtchnl_quanta_cfg);
 #define VIRTCHNL_1588_PTP_CAP_WRITE_PHC		BIT(3)
 #define VIRTCHNL_1588_PTP_CAP_PHC_REGS		BIT(4)
 #define VIRTCHNL_1588_PTP_CAP_PIN_CFG		BIT(5)
+#define VIRTCHNL_1588_PTP_CAP_SYNCE		BIT(6)
 
 /**
  * virtchnl_phc_regs
@@ -2222,6 +2275,11 @@ enum virtchnl_ptp_tstamp_format {
  * input to timestamp external events, or as an output to cause a periodic
  * signal output.
  *
+ * VIRTCHNL_1588_PTP_CAP_SYNCE indicates that the VF has access to SyncE related
+ * capabilities. The first command the VF should issue is the
+ * VIRTCHNL_OP_SYNCE_GET_HW_INFO. It returns to VF all required HW details
+ * needed for further processing.
+ *
  * Note that in the future, additional capability flags may be added which
  * indicate additional extended support. All fields marked as reserved by this
  * header will be set to zero. VF implementations should verify this to ensure
@@ -2600,6 +2658,494 @@ struct virtchnl_phc_ext_tstamp {
 
 VIRTCHNL_CHECK_STRUCT_LEN(24, virtchnl_phc_ext_tstamp);
 
+/**
+ * virtchnl_synce_get_phy_rec_clk_out
+ * @phy_output: PHY reference clock output pin
+ * @port_num: Port number
+ * @flags: PHY flags
+ * @rsvd: Reserved for future extension
+ *
+ * Structure sent with VIRTCHNL_OP_SYNCE_GET_PHY_REC_CLK_OUT. This command reads
+ * the mapping of the Ethernet lanes to the recovered clocks. The request is
+ * acceptable only when VF negotiated VIRTCHNL_1588_PTP_CAP_SYNCE capability
+ * with PF.
+ *
+ * The VF driver sets phy_output to choose CGU pin. In response the PF driver
+ * sends the same structure with the same opcode.
+ *
+ * The VF driver can also set port_num to 0xFF to check if the PHY output is
+ * driven by the PF that sends that command.
+ *
+ * If the Admin Queue command returns an error the PF will return
+ * VIRTCHNL_STATUS_ERR_ADMIN_QUEUE_ERROR with unchanged structure to VF.
+ */
+struct virtchnl_synce_get_phy_rec_clk_out {
+	u8 phy_output;
+	u8 port_num;
+#define VIRTCHNL_GET_PHY_REC_CLK_OUT_CURR_PORT	0xFF
+	u8 flags;
+#define VIRTCHNL_GET_PHY_REC_CLK_OUT_OUT_EN	BIT(0)
+	u8 rsvd[13];
+};
+
+VIRTCHNL_CHECK_STRUCT_LEN(16, virtchnl_synce_get_phy_rec_clk_out);
+
+/**
+ * virtchnl_synce_set_phy_rec_clk_out
+ * @phy_output: PHY reference clock output pin
+ * @enable: GPIO state to be applied
+ * @rsvd: Reserved for future extension
+ *
+ * Structure sent with VIRTCHNL_OP_SYNCE_SET_PHY_REC_CLK_OUT. The command maps
+ * any of the four Ethernet lanes (PHY Port number) onto the two recovered
+ * clocks (Phy output). The request is acceptable only when VF negotiated
+ * VIRTCHNL_1588_PTP_CAP_SYNCE capability with PF.
+ *
+ * The VF driver specifies either SCL or SDA pin in phy_output and whether to
+ * enable(1) or disable(0) the given pin in enable variable.
+ * In response the PF driver sends back the same structure with the same opcode.
+ *
+ * If the Admin Queue command returns an error the PF will return
+ * VIRTCHNL_STATUS_ERR_ADMIN_QUEUE_ERROR with unchanged structure to VF.
+ */
+struct virtchnl_synce_set_phy_rec_clk_out {
+	u8 phy_output;
+	u8 enable;
+	u8 rsvd[14];
+};
+
+VIRTCHNL_CHECK_STRUCT_LEN(16, virtchnl_synce_set_phy_rec_clk_out);
+
+/**
+ * virtchnl_synce_get_cgu_ref_prio
+ * @dpll_num: DPLL index
+ * @ref_idx: Reference pin index
+ * @ref_priority: Reference input priority
+ * @rsvd: Reserved for future extension
+ *
+ * Structure sent with VIRTCHNL_OP_SYNCE_GET_CGU_REF_PRIO. The command reads
+ * the currently configured priority of the selected reference clock for a given
+ * DPLL block within a given Clock Controller (DPLL) node. The request is
+ * acceptable only when VF negotiated VIRTCHNL_1588_PTP_CAP_SYNCE capability
+ * with PF.
+ *
+ * The VF driver should set dpll_num and ref_idx to choose the pin for which
+ * the ref_priority will be returned. In response the PF driver sends the same
+ * structure with the same opcode with ref_priority filled.
+ *
+ * If the Admin Queue command returns an error the PF will return
+ * VIRTCHNL_STATUS_ERR_ADMIN_QUEUE_ERROR with unchanged structure to VF.
+ */
+struct virtchnl_synce_get_cgu_ref_prio {
+	u8 dpll_num;
+	u8 ref_idx;
+	u8 ref_priority;
+	u8 rsvd[13];
+};
+
+VIRTCHNL_CHECK_STRUCT_LEN(16, virtchnl_synce_get_cgu_ref_prio);
+
+/**
+ * virtchnl_synce_set_cgu_ref_prio
+ * @dpll_num: DPLL index
+ * @ref_idx: Reference pin index
+ * @ref_priority: Reference input priority
+ * @rsvd: Reserved for future extension
+ *
+ * Structure sent with VIRTCHNL_OP_SYNCE_SET_CGU_REF_PRIO. The command
+ * configures the priority of the selected Input Index within a given DPLL block
+ * of CCU node. The request is acceptable only when VF negotiated
+ * VIRTCHNL_1588_PTP_CAP_SYNCE capability with PF.
+ *
+ * The VF driver should set dpll_num and ref_idx to choose the pin and
+ * ref_priority to be applied to given pin. In response the PF driver sends the
+ * same structure with the same opcode.
+ *
+ * If the Admin Queue command returns an error the PF will return
+ * VIRTCHNL_STATUS_ERR_ADMIN_QUEUE_ERROR with unchanged structure to VF.
+ */
+struct virtchnl_synce_set_cgu_ref_prio {
+	u8 dpll_num;
+	u8 ref_idx;
+	u8 ref_priority;
+	u8 rsvd[13];
+};
+
+VIRTCHNL_CHECK_STRUCT_LEN(16, virtchnl_synce_set_cgu_ref_prio);
+
+/**
+ * virtchnl_synce_get_input_pin_cfg
+ * @freq: Frequency of the reference clock input
+ * @phase_delay: Phase compensation for the reference clock input
+ * @input_idx: CGU pin index
+ * @status: Status flags
+ * @type: Input type flags
+ * @flags1: First set of flags
+ * @flags2: Second set of flags
+ * @rsvd: Reserved for future extension
+ *
+ * Structure sent with VIRTCHNL_OP_SYNCE_GET_INPUT_PIN_CFG. The command reads
+ * the current configuration of the specified reference clock input of a given
+ * Clock Controller (DPLL) node. The request is acceptable only when VF
+ * negotiated VIRTCHNL_1588_PTP_CAP_SYNCE capability with PF.
+ *
+ * The VF driver should set input_idx to choose CGU pin for which the
+ * configuration will be returned. In response the PF driver sends the same
+ * structure with the same opcode with the remaining fields filled.
+ *
+ * If the Admin Queue command returns an error the PF will return
+ * VIRTCHNL_STATUS_ERR_ADMIN_QUEUE_ERROR with unchanged structure to VF.
+ */
+struct virtchnl_synce_get_input_pin_cfg {
+	u32 freq;
+	u32 phase_delay;
+	u8 input_idx;
+	u8 status;
+#define VIRTCHNL_GET_CGU_IN_CFG_STATUS_LOS		BIT(0)
+#define VIRTCHNL_GET_CGU_IN_CFG_STATUS_SCM_FAIL		BIT(1)
+#define VIRTCHNL_GET_CGU_IN_CFG_STATUS_CFM_FAIL		BIT(2)
+#define VIRTCHNL_GET_CGU_IN_CFG_STATUS_GST_FAIL		BIT(3)
+#define VIRTCHNL_GET_CGU_IN_CFG_STATUS_PFM_FAIL		BIT(4)
+#define VIRTCHNL_GET_CGU_IN_CFG_STATUS_ESYNC_FAIL	BIT(6)
+#define VIRTCHNL_GET_CGU_IN_CFG_STATUS_ESYNC_CAP	BIT(7)
+	u8 type;
+#define VIRTCHNL_GET_CGU_IN_CFG_TYPE_READ_ONLY		BIT(0)
+#define VIRTCHNL_GET_CGU_IN_CFG_TYPE_GPS		BIT(4)
+#define VIRTCHNL_GET_CGU_IN_CFG_TYPE_EXTERNAL		BIT(5)
+#define VIRTCHNL_GET_CGU_IN_CFG_TYPE_PHY		BIT(6)
+	u8 flags1;
+#define VIRTCHNL_GET_CGU_IN_CFG_FLG1_PHASE_DELAY_SUPP	BIT(0)
+#define VIRTCHNL_GET_CGU_IN_CFG_FLG1_1PPS_SUPP		BIT(2)
+#define VIRTCHNL_GET_CGU_IN_CFG_FLG1_10MHZ_SUPP		BIT(3)
+#define VIRTCHNL_GET_CGU_IN_CFG_FLG1_ANYFREQ		BIT(7)
+	u8 flags2;
+#define VIRTCHNL_GET_CGU_IN_CFG_FLG2_INPUT_EN		BIT(5)
+#define VIRTCHNL_GET_CGU_IN_CFG_FLG2_ESYNC_EN		BIT(6)
+	u8 rsvd[3];
+};
+
+VIRTCHNL_CHECK_STRUCT_LEN(16, virtchnl_synce_get_input_pin_cfg);
+
+/**
+ * virtchnl_synce_set_input_pin_cfg
+ * @freq: Frequency of the reference clock input
+ * @phase_delay: Phase compensation for the reference clock input
+ * @input_idx: CGU pin index
+ * @flags1: First set of flags
+ * @flags2: Second set of flags
+ * @rsvd: Reserved for future extension
+ *
+ * Structure sent with VIRTCHNL_OP_SYNCE_SET_INPUT_PIN_CFG. The command
+ * configures the specified reference clock input of a given Clock Controller
+ * (DPLL) node. The request is acceptable only when VF negotiated
+ * VIRTCHNL_1588_PTP_CAP_SYNCE capability with PF.
+ *
+ * The VF driver should set input_idx to choose CGU pin and the rest of fields
+ * according to the required configuration. In response the PF driver sends the
+ * same structure with the same opcode.
+ *
+ * If the Admin Queue command returns an error the PF will return
+ * VIRTCHNL_STATUS_ERR_ADMIN_QUEUE_ERROR with unchanged structure to VF.
+ */
+struct virtchnl_synce_set_input_pin_cfg {
+	u32 freq;
+	u32 phase_delay;
+	u8 input_idx;
+	u8 flags1;
+#define VIRTCHNL_SET_CGU_IN_CFG_FLG1_UPDATE_FREQ	BIT(6)
+#define VIRTCHNL_SET_CGU_IN_CFG_FLG1_UPDATE_DELAY	BIT(7)
+	u8 flags2;
+#define VIRTCHNL_SET_CGU_IN_CFG_FLG2_INPUT_EN		BIT(5)
+#define VIRTCHNL_SET_CGU_IN_CFG_FLG2_ESYNC_EN		BIT(6)
+	u8 rsvd[5];
+};
+
+VIRTCHNL_CHECK_STRUCT_LEN(16, virtchnl_synce_set_input_pin_cfg);
+
+/**
+ * virtchnl_synce_get_output_pin_cfg
+ * @freq: Output frequency
+ * @src_freq: Source frequency
+ * @output_idx: Output pin index
+ * @flags: Output flags
+ * @src_sel: Internal DPLL source
+ * @rsvd: Reserved for future extension
+ *
+ * Structure sent with VIRTCHNL_OP_SYNCE_GET_OUTPUT_PIN_CFG. The command reads
+ * the current frequency, phase compensation and embedded sync configuration
+ * of the specified clock output of a given Clock Controller (DPLL) node.
+ * The request is acceptable only when VF negotiated
+ * VIRTCHNL_1588_PTP_CAP_SYNCE capability with PF.
+ *
+ * The VF driver should set output_idx to choose CGU pin and the rest of fields
+ * according to the required configuration. In response the PF driver sends the
+ * same structure with the same opcode.
+ *
+ * If the Admin Queue command returns an error the PF will return
+ * VIRTCHNL_STATUS_ERR_ADMIN_QUEUE_ERROR with unchanged structure to VF.
+ */
+struct virtchnl_synce_get_output_pin_cfg {
+	u32 freq;
+	u32 src_freq;
+	u8 output_idx;
+	u8 flags;
+#define VIRTCHNL_GET_CGU_OUT_CFG_OUT_EN		BIT(0)
+#define VIRTCHNL_GET_CGU_OUT_CFG_ESYNC_EN	BIT(1)
+#define VIRTCHNL_GET_CGU_OUT_CFG_ESYNC_ABILITY	BIT(2)
+	u8 src_sel;
+#define VIRTCHNL_GET_CGU_OUT_CFG_DPLL_SRC_SEL_SHIFT	0
+#define VIRTCHNL_GET_CGU_OUT_CFG_DPLL_SRC_SEL \
+	(0x1F << VIRTCHNL_GET_CGU_OUT_CFG_DPLL_SRC_SEL_SHIFT)
+#define VIRTCHNL_GET_CGU_OUT_CFG_DPLL_MODE_SHIFT	5
+#define VIRTCHNL_GET_CGU_OUT_CFG_DPLL_MODE \
+	(0x7 << VIRTCHNL_GET_CGU_OUT_CFG_DPLL_MODE_SHIFT)
+	u8 rsvd[5];
+};
+
+VIRTCHNL_CHECK_STRUCT_LEN(16, virtchnl_synce_get_output_pin_cfg);
+
+/**
+ * virtchnl_synce_set_output_pin_cfg
+ * @freq: Output frequency
+ * @phase_delay: Output phase compensation
+ * @output_idx: Output pin index
+ * @flags: Output flags
+ * @src_sel: Internal DPLL source
+ * @rsvd: Reserved for future extension
+ *
+ * Structure sent with VIRTCHNL_OP_SYNCE_SET_OUTPUT_PIN_CFG. The command
+ * configures the specified reference clock input of a given Clock Controller
+ * (DPLL) node. The request is acceptable only when VF negotiated
+ * VIRTCHNL_1588_PTP_CAP_SYNCE capability with PF.
+ *
+ * The VF driver should set output_idx to choose CGU pin and the rest of fields
+ * according to the required configuration. In response the PF driver sends the
+ * same structure with the same opcode.
+ *
+ * If the Admin Queue command returns an error the PF will return
+ * VIRTCHNL_STATUS_ERR_ADMIN_QUEUE_ERROR with unchanged structure to VF.
+ */
+struct virtchnl_synce_set_output_pin_cfg {
+	u32 freq;
+	u32 phase_delay;
+	u8 output_idx;
+	u8 flags;
+#define VIRTCHNL_SET_CGU_OUT_CFG_OUT_EN		BIT(0)
+#define VIRTCHNL_SET_CGU_OUT_CFG_ESYNC_EN	BIT(1)
+#define VIRTCHNL_SET_CGU_OUT_CFG_UPDATE_FREQ	BIT(2)
+#define VIRTCHNL_SET_CGU_OUT_CFG_UPDATE_PHASE	BIT(3)
+#define VIRTCHNL_SET_CGU_OUT_CFG_UPDATE_SRC_SEL	BIT(4)
+	u8 src_sel;
+#define VIRTCHNL_SET_CGU_OUT_CFG_DPLL_SRC_SEL	0x1F
+	u8 rsvd[5];
+};
+
+VIRTCHNL_CHECK_STRUCT_LEN(16, virtchnl_synce_set_output_pin_cfg);
+
+/**
+ * virtchnl_synce_get_cgu_abilities
+ * @num_inputs: Number of Clock Controller inputs
+ * @num_outputs: Number of Clock Controller outputs
+ * @pps_dpll_idx: The index of a PPS DPLL block in the CCU
+ * @synce_dpll_idx: The index of a SyncE DPLL block in the CCU
+ * @max_in_freq: Maximum Input Frequency
+ * @max_in_phase_adj: Maximum Input Phase Adjustment
+ * @max_out_freq: Maximum Output Frequency
+ * @max_out_phase_adj: Maximum Output Phase Adjustment
+ * @cgu_part_num: Clock Controller Part Number
+ * @rsvd: Reserved for future extension
+ *
+ * Structure sent with VIRTCHNL_OP_SYNCE_GET_CGU_ABILITIES. The command reads
+ * the capabilities of the CC. If the value is not defined or cannot be
+ * evaluated, then it shall be 0xFF for 8-bit fields and 0xFFFFFFFF for 32-bit
+ * fields. The request is acceptable only when VF negotiated
+ * VIRTCHNL_1588_PTP_CAP_SYNCE capability with PF.
+ *
+ * The VF driver sends an empty message to the PF driver. In response the PF
+ * driver sends the virtchnl_synce_get_cgu_abilities structure.
+ *
+ * If the Admin Queue command returns an error the PF will return
+ * VIRTCHNL_STATUS_ERR_ADMIN_QUEUE_ERROR with unchanged structure to VF.
+ */
+struct virtchnl_synce_get_cgu_abilities {
+	u8 num_inputs;
+	u8 num_outputs;
+	u8 pps_dpll_idx;
+	u8 synce_dpll_idx;
+	u32 max_in_freq;
+	u32 max_in_phase_adj;
+	u32 max_out_freq;
+	u32 max_out_phase_adj;
+	u8 cgu_part_num;
+	u8 rsvd[3];
+};
+
+VIRTCHNL_CHECK_STRUCT_LEN(24, virtchnl_synce_get_cgu_abilities);
+
+/**
+ * virtchnl_synce_get_cgu_dpll_status
+ * @phase_offset: Phase offset in ns
+ * @dpll_state: DPLL state
+ * @dpll_num: DPLL index
+ * @ref_state: Reference clock state
+ * @eec_mode: EEC Mode - The configured clock quality level
+ * @rsvd: Reserved for future extension
+ *
+ * Structure sent with VIRTCHNL_OP_SYNCE_GET_CGU_DPLL_STATUS. The command reads
+ * the selected DPLL block status within the selected CCU node. The request is
+ * acceptable only when VF negotiated VIRTCHNL_1588_PTP_CAP_SYNCE capability
+ * with PF.
+ *
+ * The VF driver chooses in dpll_num which DPLL block it wants to read.
+ * In response the PF driver fills the remaining fields in structure and sends
+ * to VF with the same opcode.
+ *
+ * If the Admin Queue command returns an error the PF will return
+ * VIRTCHNL_STATUS_ERR_ADMIN_QUEUE_ERROR with unchanged structure to VF.
+ */
+struct virtchnl_synce_get_cgu_dpll_status {
+	s64 phase_offset;
+	u16 dpll_state;
+#define VIRTCHNL_GET_CGU_DPLL_STATUS_STATE_LOCK			BIT(0)
+#define VIRTCHNL_GET_CGU_DPLL_STATUS_STATE_HO			BIT(1)
+#define VIRTCHNL_GET_CGU_DPLL_STATUS_STATE_HO_READY		BIT(2)
+#define VIRTCHNL_GET_CGU_DPLL_STATUS_STATE_FLHIT		BIT(5)
+#define VIRTCHNL_GET_CGU_DPLL_STATUS_STATE_PSLHIT		BIT(7)
+#define VIRTCHNL_GET_CGU_DPLL_STATUS_STATE_CLK_REF_SHIFT	8
+#define VIRTCHNL_GET_CGU_DPLL_STATUS_STATE_CLK_REF_SEL	\
+	(0x1F << VIRTCHNL_GET_CGU_DPLL_STATUS_STATE_CLK_REF_SHIFT)
+#define VIRTCHNL_GET_CGU_DPLL_STATUS_STATE_MODE_SHIFT		13
+#define VIRTCHNL_GET_CGU_DPLL_STATUS_STATE_MODE \
+	(0x7 << VIRTCHNL_GET_CGU_DPLL_STATUS_STATE_MODE_SHIFT)
+	u8 dpll_num;
+	u8 ref_state;
+#define VIRTCHNL_GET_CGU_DPLL_STATUS_REF_SW_LOS			BIT(0)
+#define VIRTCHNL_GET_CGU_DPLL_STATUS_REF_SW_SCM			BIT(1)
+#define VIRTCHNL_GET_CGU_DPLL_STATUS_REF_SW_CFM			BIT(2)
+#define VIRTCHNL_GET_CGU_DPLL_STATUS_REF_SW_GST			BIT(3)
+#define VIRTCHNL_GET_CGU_DPLL_STATUS_REF_SW_PFM			BIT(4)
+#define VIRTCHNL_GET_CGU_DPLL_STATUS_FAST_LOCK_EN		BIT(5)
+#define VIRTCHNL_GET_CGU_DPLL_STATUS_REF_SW_ESYNC		BIT(6)
+	u8 eec_mode;
+#define VIRTCHNL_GET_CGU_DPLL_STATUS_EEC_MODE_1			0xA
+#define VIRTCHNL_GET_CGU_DPLL_STATUS_EEC_MODE_2			0xB
+#define VIRTCHNL_GET_CGU_DPLL_STATUS_EEC_MODE_UNKNOWN		0xF
+	u8 rsvd[11];
+};
+
+VIRTCHNL_CHECK_STRUCT_LEN(24, virtchnl_synce_get_cgu_dpll_status);
+
+/**
+ * virtchnl_synce_set_cgu_dpll_config
+ * @dpll_num: DPLL index
+ * @ref_state: Reference clock state
+ * @config: DPLL config
+ * @eec_mode: EEC Mode - The configured clock quality level
+ * @rsvd: Reserved for future extension
+ *
+ * Structure sent with VIRTCHNL_OP_SYNCE_SET_CGU_DPLL_CONFIG. The command
+ * configures the selected DPLL block within the selected CCU node. The request
+ * is acceptable only when VF negotiated VIRTCHNL_1588_PTP_CAP_SYNCE
+ * capability with PF.
+ *
+ * The VF driver chooses in dpll_num which DPLL block it wants to configure.
+ * The PF driver applies the given configuration and returns unchanged structure
+ * to the VF.
+ *
+ * If the Admin Queue command returns an error the PF will return
+ * VIRTCHNL_STATUS_ERR_ADMIN_QUEUE_ERROR with unchanged structure to VF.
+ */
+struct virtchnl_synce_set_cgu_dpll_config {
+	u8 dpll_num;
+	u8 ref_state;
+#define VIRTCHNL_SET_CGU_DPLL_CONFIG_REF_SW_LOS		BIT(0)
+#define VIRTCHNL_SET_CGU_DPLL_CONFIG_REF_SW_SCM		BIT(1)
+#define VIRTCHNL_SET_CGU_DPLL_CONFIG_REF_SW_CFM		BIT(2)
+#define VIRTCHNL_SET_CGU_DPLL_CONFIG_REF_SW_GST		BIT(3)
+#define VIRTCHNL_SET_CGU_DPLL_CONFIG_REF_SW_PFM		BIT(4)
+#define VIRTCHNL_SET_CGU_DPLL_CONFIG_REF_FLOCK_EN	BIT(5)
+#define VIRTCHNL_SET_CGU_DPLL_CONFIG_REF_SW_ESYNC	BIT(6)
+	u8 config;
+#define VIRTCHNL_SET_CGU_DPLL_CONFIG_CLK_REF_SEL	0x1F
+#define VIRTCHNL_SET_CGU_DPLL_CONFIG_MODE		(0x7 << 5)
+	u8 eec_mode;
+	u8 rsvd[12];
+};
+
+VIRTCHNL_CHECK_STRUCT_LEN(16, virtchnl_synce_set_cgu_dpll_config);
+
+/**
+ * virtchnl_synce_get_cgu_info
+ * @cgu_id: CGU ID
+ * @cgu_cfg_ver: CGU config version
+ * @cgu_fw_ver: CGU firmware version
+ * @rsvd: Reserved for future extension
+ *
+ * Structure sent with VIRTCHNL_OP_SYNCE_GET_CGU_INFO. The command retrieves
+ * information about CCU. If parameter is unsupported, then it should contain
+ * 0xFFFFFFFF for 32-bit values or 0xFF for 8-bit values. The request is
+ * acceptable only when VF negotiated VIRTCHNL_1588_PTP_CAP_SYNCE capability
+ * with PF.
+ *
+ * The VF driver sends an empty message to the PF driver. In response the PF
+ * driver sends the virtchnl_synce_get_cgu_info structure.
+ *
+ * If the Admin Queue command returns an error the PF will return
+ * VIRTCHNL_STATUS_ERR_ADMIN_QUEUE_ERROR with unchanged structure to VF.
+ */
+struct virtchnl_synce_get_cgu_info {
+	u32 cgu_id;
+	u32 cgu_cfg_ver;
+	u32 cgu_fw_ver;
+	u8 rsvd[4];
+};
+
+VIRTCHNL_CHECK_STRUCT_LEN(16, virtchnl_synce_get_cgu_info);
+
+/**
+ * virtchnl_cgu_pin
+ * @pin_index: Pin index to use in all functions
+ * @name: Human readable pin name
+ *
+ * Structure used as a part of VIRTCHNL_OP_SYNCE_GET_HW_INFO request.
+ * The VF issues a VIRTCHNL_OP_SYNCE_GET_HW_INFO request to the PF in
+ * order to obtain the list of available CGU pins.
+ */
+struct virtchnl_cgu_pin {
+	u8 pin_index;
+	char name[63];
+};
+
+VIRTCHNL_CHECK_STRUCT_LEN(64, virtchnl_cgu_pin);
+
+/**
+ * virtchnl_synce_get_hw_info
+ * @cgu_present: True if CGU is present
+ * @rclk_present: True is PHY recovered clock is present
+ * @c827_idx: C827 index for the current port
+ * @len: Length of the variable CGU pins array
+ * @rsvd: Reserved for future extension
+ * @pins: Variable length CGU pins array
+ *
+ * Variable structure sent by the PF in reply to VIRTCHNL_OP_SYNCE_GET_HW_INFO.
+ * The VF does not send this structure with its request of the operation.
+ * The request is acceptable only when VF negotiated
+ * VIRTCHNL_1588_PTP_CAP_SYNCE capability with PF.
+ *
+ * If this opcode returns error status the VF should assume it does not have
+ * access to any other SyncE commands.
+ */
+struct virtchnl_synce_get_hw_info {
+	u8 cgu_present;
+	u8 rclk_present;
+	u8 c827_idx;
+	u8 len;
+	u8 rsvd[4];
+	struct virtchnl_cgu_pin pins[1];
+};
+
+VIRTCHNL_CHECK_STRUCT_LEN(72, virtchnl_synce_get_hw_info);
+
 /* Since VF messages are limited by u16 size, precalculate the maximum possible
  * values of nested elements in virtchnl structures that virtual channel can
  * possibly handle in a single message.
@@ -2918,6 +3464,42 @@ virtchnl_vc_validate_vf_msg(struct virtchnl_version_info *ver, u32 v_opcode,
 	case VIRTCHNL_OP_1588_PTP_EXT_TIMESTAMP:
 		valid_len = sizeof(struct virtchnl_phc_ext_tstamp);
 		break;
+	case VIRTCHNL_OP_SYNCE_GET_PHY_REC_CLK_OUT:
+		valid_len = sizeof(struct virtchnl_synce_get_phy_rec_clk_out);
+		break;
+	case VIRTCHNL_OP_SYNCE_SET_PHY_REC_CLK_OUT:
+		valid_len = sizeof(struct virtchnl_synce_set_phy_rec_clk_out);
+		break;
+	case VIRTCHNL_OP_SYNCE_GET_CGU_REF_PRIO:
+		valid_len = sizeof(struct virtchnl_synce_get_cgu_ref_prio);
+		break;
+	case VIRTCHNL_OP_SYNCE_SET_CGU_REF_PRIO:
+		valid_len = sizeof(struct virtchnl_synce_set_cgu_ref_prio);
+		break;
+	case VIRTCHNL_OP_SYNCE_GET_INPUT_PIN_CFG:
+		valid_len = sizeof(struct virtchnl_synce_get_input_pin_cfg);
+		break;
+	case VIRTCHNL_OP_SYNCE_SET_INPUT_PIN_CFG:
+		valid_len = sizeof(struct virtchnl_synce_set_input_pin_cfg);
+		break;
+	case VIRTCHNL_OP_SYNCE_GET_OUTPUT_PIN_CFG:
+		valid_len = sizeof(struct virtchnl_synce_get_output_pin_cfg);
+		break;
+	case VIRTCHNL_OP_SYNCE_SET_OUTPUT_PIN_CFG:
+		valid_len = sizeof(struct virtchnl_synce_set_output_pin_cfg);
+		break;
+	case VIRTCHNL_OP_SYNCE_GET_CGU_ABILITIES:
+		break;
+	case VIRTCHNL_OP_SYNCE_GET_CGU_DPLL_STATUS:
+		valid_len = sizeof(struct virtchnl_synce_get_cgu_dpll_status);
+		break;
+	case VIRTCHNL_OP_SYNCE_SET_CGU_DPLL_CONFIG:
+		valid_len = sizeof(struct virtchnl_synce_set_cgu_dpll_config);
+		break;
+	case VIRTCHNL_OP_SYNCE_GET_CGU_INFO:
+		break;
+	case VIRTCHNL_OP_SYNCE_GET_HW_INFO:
+		break;
 	case VIRTCHNL_OP_ENABLE_QUEUES_V2:
 	case VIRTCHNL_OP_DISABLE_QUEUES_V2:
 		valid_len = sizeof(struct virtchnl_del_ena_dis_queues);
