From patchwork Tue Apr 11 09:11:37 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nithin Dabilpuram X-Patchwork-Id: 125919 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id A51F44291B; Tue, 11 Apr 2023 11:13:37 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id BAE9642D4A; Tue, 11 Apr 2023 11:12:44 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id E694B41141 for ; Tue, 11 Apr 2023 11:12:43 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 33B8UBi6021423 for ; Tue, 11 Apr 2023 02:12:43 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=0GiTkWCZQ0JJs8iGB/nny2WYlrJmKP7MD9Qe2wcYG1A=; b=VQY5HkMsI8kp1r0+Ukw1syC1sQPe6TwXpyVaC+Mnva+Vpf+Ifswg0bGeNEyrgovfEQEG gth3QwD3ctUx+H2qPXF6sJBnV543fx2QbezKb5egjzufMl6OrLRmCZ6jLFko4ZI0J3zW MerZXi1azMTy3b1tlxpFIXNSZ/L1sbAkBJTf2uCMUwjjuXPzO3HOfe6mEU8SepuhSiZ7 B4phBueLMUuxzIxixfSMUSsy8W2+/ZlC/QzvbwOpGw3THaM4WYNrpC6w7gmAwbK9LfTy /5+bReF9JItX2wqaFThyjmNDi0gnQG+lY1ie+hRHvSyYymXCpb7jbGsqKgyGh6yfiZ/y yQ== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3pvt73b1v4-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Tue, 11 Apr 2023 02:12:43 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.48; Tue, 11 Apr 2023 02:12:41 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.48 via Frontend Transport; Tue, 11 Apr 2023 02:12:41 -0700 Received: from hyd1588t430.caveonetworks.com (unknown [10.29.52.204]) by maili.marvell.com (Postfix) with ESMTP id 35E3A3F706A; Tue, 11 Apr 2023 02:12:38 -0700 (PDT) From: Nithin Dabilpuram To: Nithin Kumar Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao CC: , Subject: [PATCH 14/21] common/cnxk: avoid STALL with dual rate on CNF95N Date: Tue, 11 Apr 2023 14:41:37 +0530 Message-ID: <20230411091144.1087887-14-ndabilpuram@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230411091144.1087887-1-ndabilpuram@marvell.com> References: <20230411091144.1087887-1-ndabilpuram@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: 3_dZ0nPGeZkmzS71t8AUN4iKPqwVOm8z X-Proofpoint-ORIG-GUID: 3_dZ0nPGeZkmzS71t8AUN4iKPqwVOm8z X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.942,Hydra:6.0.573,FMLib:17.11.170.22 definitions=2023-04-11_05,2023-04-06_03,2023-02-09_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Satha Rao Due to errata RED_ALGO STALL with dual shaper rate will hangs on platforms CNF95N and CNF95O. Set READ_ALGO to DISCARD with dual shaper rate on CNF95N and CNF95O. Signed-off-by: Satha Rao --- drivers/common/cnxk/roc_nix_tm_utils.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/common/cnxk/roc_nix_tm_utils.c b/drivers/common/cnxk/roc_nix_tm_utils.c index 9ede1bebe7..3840d6d457 100644 --- a/drivers/common/cnxk/roc_nix_tm_utils.c +++ b/drivers/common/cnxk/roc_nix_tm_utils.c @@ -1267,7 +1267,8 @@ roc_nix_tm_shaper_default_red_algo(struct roc_nix_tm_node *node, tm_node->red_algo = roc_prof->red_algo; /* C0 doesn't support STALL when both PIR & CIR are enabled */ - if (roc_model_is_cn96_cx()) { + if (roc_model_is_cn96_cx() || roc_model_is_cnf95xxn_a0() || roc_model_is_cnf95xxo_a0() || + roc_model_is_cnf95xxn_a1() || roc_model_is_cnf95xxn_b0()) { nix_tm_shaper_conf_get(profile, &cir, &pir); if (pir.rate && cir.rate)