[1/2] net/cnxk: optimize flow control hysteresis
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Commit Message
From: Pavan Nikhilesh <pbhagavatula@marvell.com>
Set flow control hysteresis to ignore immediate sequence of
decrement-increment to avoid unnecessary LLC traffic.
Enable hysteresis when SQ length is more than 512 as it lower
queue lengths will require faster updates.
Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
Signed-off-by: Satha Rao <skoteshwar@marvell.com>
---
drivers/net/cnxk/cnxk_ethdev.c | 2 ++
drivers/net/cnxk/cnxk_ethdev.h | 2 ++
2 files changed, 4 insertions(+)
Comments
On Tue, Apr 11, 2023 at 12:31 PM <pbhagavatula@marvell.com> wrote:
>
> From: Pavan Nikhilesh <pbhagavatula@marvell.com>
>
> Set flow control hysteresis to ignore immediate sequence of
> decrement-increment to avoid unnecessary LLC traffic.
> Enable hysteresis when SQ length is more than 512 as it lower
> queue lengths will require faster updates.
>
> Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
Series applied to dpdk-next-net-mrvl/for-next-net. Thanks
> Signed-off-by: Satha Rao <skoteshwar@marvell.com>
> ---
> drivers/net/cnxk/cnxk_ethdev.c | 2 ++
> drivers/net/cnxk/cnxk_ethdev.h | 2 ++
> 2 files changed, 4 insertions(+)
>
> diff --git a/drivers/net/cnxk/cnxk_ethdev.c b/drivers/net/cnxk/cnxk_ethdev.c
> index 1cae3084e1..42a52ed0ca 100644
> --- a/drivers/net/cnxk/cnxk_ethdev.c
> +++ b/drivers/net/cnxk/cnxk_ethdev.c
> @@ -487,6 +487,8 @@ cnxk_nix_tx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t qid,
> sq->qid = qid;
> sq->nb_desc = nb_desc;
> sq->max_sqe_sz = nix_sq_max_sqe_sz(dev);
> + if (sq->nb_desc >= CNXK_NIX_DEF_SQ_COUNT)
> + sq->fc_hyst_bits = 0x1;
>
> if (nix->tx_compl_ena) {
> sq->cqid = sq->qid + dev->nb_rxq;
> diff --git a/drivers/net/cnxk/cnxk_ethdev.h b/drivers/net/cnxk/cnxk_ethdev.h
> index 62a06e5d03..97537de17a 100644
> --- a/drivers/net/cnxk/cnxk_ethdev.h
> +++ b/drivers/net/cnxk/cnxk_ethdev.h
> @@ -49,6 +49,8 @@
> /* LPB & SPB */
> #define CNXK_NIX_NUM_POOLS_MAX 2
>
> +#define CNXK_NIX_DEF_SQ_COUNT 512
> +
> #define CNXK_NIX_RSS_L3_L4_SRC_DST \
> (RTE_ETH_RSS_L3_SRC_ONLY | RTE_ETH_RSS_L3_DST_ONLY | \
> RTE_ETH_RSS_L4_SRC_ONLY | RTE_ETH_RSS_L4_DST_ONLY)
> --
> 2.25.1
>
@@ -487,6 +487,8 @@ cnxk_nix_tx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t qid,
sq->qid = qid;
sq->nb_desc = nb_desc;
sq->max_sqe_sz = nix_sq_max_sqe_sz(dev);
+ if (sq->nb_desc >= CNXK_NIX_DEF_SQ_COUNT)
+ sq->fc_hyst_bits = 0x1;
if (nix->tx_compl_ena) {
sq->cqid = sq->qid + dev->nb_rxq;
@@ -49,6 +49,8 @@
/* LPB & SPB */
#define CNXK_NIX_NUM_POOLS_MAX 2
+#define CNXK_NIX_DEF_SQ_COUNT 512
+
#define CNXK_NIX_RSS_L3_L4_SRC_DST \
(RTE_ETH_RSS_L3_SRC_ONLY | RTE_ETH_RSS_L3_DST_ONLY | \
RTE_ETH_RSS_L4_SRC_ONLY | RTE_ETH_RSS_L4_DST_ONLY)