From patchwork Tue Apr 4 14:18:52 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sathesh B Edara X-Patchwork-Id: 125780 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id C3E9C428CE; Tue, 4 Apr 2023 16:20:06 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id EBB8042D40; Tue, 4 Apr 2023 16:19:14 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id 811D542D35 for ; Tue, 4 Apr 2023 16:19:13 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 334ApmU6017569 for ; Tue, 4 Apr 2023 07:19:13 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=PxEW4SEKHaMTnuHrueLKIucRIej85tUIjX/Vf68Wh7Y=; b=jbzkS7lFx7iz3bMTddodkOlR3GV2DBOyLBwwrtcpq0ug78q+h+VCBKLZrbynt9t0F6Sw qClzmoTh1hhpGV1I6tXG9uXZCXsBbBpFEk3g6CI0VL9Ua7ZAvgao+FEgrcTZpvRLBQir LmMyTbp4K9zeiw3K/0ZvTy1wa+UWnhReh3s4Eo5sPa7WhYZXP0DOz4vfGIcUrikj1Lrs zZ2y/wn/Y+KVCIJ1nTOcbQTQ2+GyQfEKTrfP0uFSVbxnyOJyYhb46JC2HVugsu5lT1R6 NekQE6MJ8r8uqfgf4k/dGc8tQTUyycaluhZKEv/oNRHoEy9cFb/YQFekV2TYcOaultuB sQ== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3ppm4qw0wt-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Tue, 04 Apr 2023 07:19:12 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.48; Tue, 4 Apr 2023 07:19:10 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.48 via Frontend Transport; Tue, 4 Apr 2023 07:19:10 -0700 Received: from localhost.marvell.com (unknown [10.106.27.249]) by maili.marvell.com (Postfix) with ESMTP id EFA1B5B6930; Tue, 4 Apr 2023 07:19:09 -0700 (PDT) From: Sathesh Edara To: , , , "Radha Mohan Chintakuntla" , Veerasenareddy Burru CC: Subject: [PATCH v1 7/9] net/octeon_ep: update queue size checks Date: Tue, 4 Apr 2023 07:18:52 -0700 Message-ID: <20230404141855.1025625-8-sedara@marvell.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20230404141855.1025625-1-sedara@marvell.com> References: <20230404141855.1025625-1-sedara@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: i1NM-tcfgEeEZOfif70GT5JbrHiCi72I X-Proofpoint-GUID: i1NM-tcfgEeEZOfif70GT5JbrHiCi72I X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.942,Hydra:6.0.573,FMLib:17.11.170.22 definitions=2023-04-04_06,2023-04-04_04,2023-02-09_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org This patch updates the output queue size checks to ensure that queue is larger than backpressure watermark.Add setting of default queue sizes to the minimum so that applications like testpmd can be started without explicit queue size arguments. Signed-off-by: Sathesh Edara --- drivers/net/octeon_ep/otx_ep_common.h | 9 +++++++-- drivers/net/octeon_ep/otx_ep_ethdev.c | 12 ++++++++++-- drivers/net/octeon_ep/otx_ep_rxtx.h | 4 ++-- 3 files changed, 19 insertions(+), 6 deletions(-) diff --git a/drivers/net/octeon_ep/otx_ep_common.h b/drivers/net/octeon_ep/otx_ep_common.h index 1d9da5954e..3beec71968 100644 --- a/drivers/net/octeon_ep/otx_ep_common.h +++ b/drivers/net/octeon_ep/otx_ep_common.h @@ -11,8 +11,13 @@ #define OTX_EP_MAX_RINGS_PER_VF (8) #define OTX_EP_CFG_IO_QUEUES OTX_EP_MAX_RINGS_PER_VF #define OTX_EP_64BYTE_INSTR (64) -#define OTX_EP_MIN_IQ_DESCRIPTORS (128) -#define OTX_EP_MIN_OQ_DESCRIPTORS (128) +/* + * Backpressure for SDP is configured on Octeon, and the minimum queue sizes + * must be much larger than the backpressure watermark configured in the Octeon + * SDP driver. IQ and OQ backpressure configurations are separate. + */ +#define OTX_EP_MIN_IQ_DESCRIPTORS (2048) +#define OTX_EP_MIN_OQ_DESCRIPTORS (2048) #define OTX_EP_MAX_IQ_DESCRIPTORS (8192) #define OTX_EP_MAX_OQ_DESCRIPTORS (8192) #define OTX_EP_OQ_BUF_SIZE (2048) diff --git a/drivers/net/octeon_ep/otx_ep_ethdev.c b/drivers/net/octeon_ep/otx_ep_ethdev.c index f1f2d2ba18..2cf82bd2e4 100644 --- a/drivers/net/octeon_ep/otx_ep_ethdev.c +++ b/drivers/net/octeon_ep/otx_ep_ethdev.c @@ -47,6 +47,9 @@ otx_ep_dev_info_get(struct rte_eth_dev *eth_dev, devinfo->rx_desc_lim = otx_ep_rx_desc_lim; devinfo->tx_desc_lim = otx_ep_tx_desc_lim; + devinfo->default_rxportconf.ring_size = OTX_EP_MIN_OQ_DESCRIPTORS; + devinfo->default_txportconf.ring_size = OTX_EP_MIN_IQ_DESCRIPTORS; + return 0; } @@ -273,8 +276,8 @@ otx_ep_rx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t q_no, return -EINVAL; } if (num_rx_descs < (SDP_GBL_WMARK * 8)) { - otx_ep_err("Invalid rx desc number should at least be greater than 8xwmark %u\n", - num_rx_descs); + otx_ep_err("Invalid rx desc number(%u) should at least be greater than 8xwmark %u\n", + num_rx_descs, (SDP_GBL_WMARK * 8)); return -EINVAL; } @@ -356,6 +359,11 @@ otx_ep_tx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t q_no, num_tx_descs); return -EINVAL; } + if (num_tx_descs < (SDP_GBL_WMARK * 8)) { + otx_ep_err("Invalid tx desc number(%u) should at least be greater than 8*wmark(%u)\n", + num_tx_descs, (SDP_GBL_WMARK * 8)); + return -EINVAL; + } retval = otx_ep_setup_iqs(otx_epvf, q_no, num_tx_descs, socket_id); diff --git a/drivers/net/octeon_ep/otx_ep_rxtx.h b/drivers/net/octeon_ep/otx_ep_rxtx.h index 1527d350b5..7012888100 100644 --- a/drivers/net/octeon_ep/otx_ep_rxtx.h +++ b/drivers/net/octeon_ep/otx_ep_rxtx.h @@ -7,8 +7,8 @@ #include -#define OTX_EP_RXD_ALIGN 1 -#define OTX_EP_TXD_ALIGN 1 +#define OTX_EP_RXD_ALIGN 2 +#define OTX_EP_TXD_ALIGN 2 #define OTX_EP_IQ_SEND_FAILED (-1) #define OTX_EP_IQ_SEND_SUCCESS (0)