net/mlx5/hws: fix IPv4 frag matching
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Commit Message
From: Hamdan Igbaria <hamdani@nvidia.com>
Fix IPv4 frag matching in case fragment_offset field is set
to non zero value in the mask.
fragment_offset value is converted using the following logic:
-In case fragment_offset value was set to 0x3fff, then we will
match only on ip_fragmented bit.
-Otherwise we will match fragment_offset based on spec and last
same as any other field.
Fixes: c55c2bf35333 ("net/mlx5/hws: add definer layer")
Cc: stable@dpdk.org
Signed-off-by: Hamdan Igbaria <hamdani@nvidia.com>
Reviewed-by: Alex Vesker <valex@nvidia.com>
Acked-by: Matan Azrad matan@nvidia.com
---
drivers/net/mlx5/hws/mlx5dr_definer.c | 11 +++++++++--
drivers/net/mlx5/hws/mlx5dr_definer.h | 9 +++++++--
2 files changed, 16 insertions(+), 4 deletions(-)
Comments
Hi,
> -----Original Message-----
> From: Alex Vesker <valex@nvidia.com>
> Sent: Thursday, March 23, 2023 2:34 PM
> To: Alex Vesker <valex@nvidia.com>; Slava Ovsiienko
> <viacheslavo@nvidia.com>; NBU-Contact-Thomas Monjalon (EXTERNAL)
> <thomas@monjalon.net>; Suanming Mou <suanmingm@nvidia.com>; Matan
> Azrad <matan@nvidia.com>
> Cc: dev@dpdk.org; Ori Kam <orika@nvidia.com>; Hamdan Igbaria
> <hamdani@nvidia.com>; stable@dpdk.org
> Subject: [PATCH] net/mlx5/hws: fix IPv4 frag matching
>
> From: Hamdan Igbaria <hamdani@nvidia.com>
>
> Fix IPv4 frag matching in case fragment_offset field is set to non zero value in
> the mask.
> fragment_offset value is converted using the following logic:
> -In case fragment_offset value was set to 0x3fff, then we will match only on
> ip_fragmented bit.
> -Otherwise we will match fragment_offset based on spec and last same as any
> other field.
>
> Fixes: c55c2bf35333 ("net/mlx5/hws: add definer layer")
> Cc: stable@dpdk.org
>
> Signed-off-by: Hamdan Igbaria <hamdani@nvidia.com>
> Reviewed-by: Alex Vesker <valex@nvidia.com>
> Acked-by: Matan Azrad matan@nvidia.com
Fixed Acked-by tag,
Patch applied to next-net-mlx,
Kindest regards,
Raslan Darawsheh
@@ -127,6 +127,7 @@ struct mlx5dr_definer_conv_data {
X(SET, ipv4_version, STE_IPV4, rte_ipv4_hdr) \
X(SET_BE16, ipv4_frag, v->fragment_offset, rte_ipv4_hdr) \
X(SET_BE16, ipv4_len, v->total_length, rte_ipv4_hdr) \
+ X(SET, ip_fragmented, !!v->fragment_offset, rte_ipv4_hdr) \
X(SET_BE16, ipv6_payload_len, v->hdr.payload_len, rte_flow_item_ipv6) \
X(SET, ipv6_proto, v->hdr.proto, rte_flow_item_ipv6) \
X(SET, ipv6_routing_hdr, IPPROTO_ROUTING, rte_flow_item_ipv6) \
@@ -735,8 +736,14 @@ mlx5dr_definer_conv_item_ipv4(struct mlx5dr_definer_conv_data *cd,
if (m->fragment_offset) {
fc = &cd->fc[DR_CALC_FNAME(IP_FRAG, inner)];
fc->item_idx = item_idx;
- fc->tag_set = &mlx5dr_definer_ipv4_frag_set;
- DR_CALC_SET(fc, eth_l3, fragment_offset, inner);
+ if (rte_be_to_cpu_16(m->fragment_offset) == 0x3fff) {
+ fc->tag_set = &mlx5dr_definer_ip_fragmented_set;
+ DR_CALC_SET(fc, eth_l2, ip_fragmented, inner);
+ } else {
+ fc->is_range = l && l->fragment_offset;
+ fc->tag_set = &mlx5dr_definer_ipv4_frag_set;
+ DR_CALC_SET(fc, eth_l3, ipv4_frag, inner);
+ }
}
if (m->next_proto_id) {
@@ -226,8 +226,13 @@ struct mlx5_ifc_definer_hl_eth_l3_bits {
u8 time_to_live_hop_limit[0x8];
u8 protocol_next_header[0x8];
u8 identification[0x10];
- u8 flags[0x3];
- u8 fragment_offset[0xd];
+ union {
+ u8 ipv4_frag[0x10];
+ struct {
+ u8 flags[0x3];
+ u8 fragment_offset[0xd];
+ };
+ };
u8 ipv4_total_length[0x10];
u8 checksum[0x10];
u8 reserved_at_60[0xc];