From patchwork Wed Feb 1 07:58:57 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Suresh Narayane, Harshad" X-Patchwork-Id: 122799 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 150CB41B9B; Wed, 1 Feb 2023 09:00:15 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id A4DA94113F; Wed, 1 Feb 2023 09:00:14 +0100 (CET) Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by mails.dpdk.org (Postfix) with ESMTP id 6CECB4021F for ; Wed, 1 Feb 2023 09:00:13 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1675238413; x=1706774413; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=P6EAcJg+oc5dcGsGcXTWO2t1e6yFaqCK0qTg389QC9g=; b=gZx21DvkGANTyDcE5VyADLL/dmQiliLlvJpdJ3JcP2KNmHCgEMHurX/Z GUz9bUStqhBcqzvkh9weGBSTia1edY+MOfXQ7Q2wuXjqrMKlEYE53Lw8b 4KKLI9elmpaplnIdjQyta3HBdmb8VoteJjvAGfGVvotvZHaLxaVqHNPoc 0XXMYtHmVMJIjK5n0LD6MDS3rALSEKAx5DehY0iiL5tK66j+CctovM/ad jYgdxVkiJ0iBI3QSDdn6IbQsS76A/sCNg56sC0FGJzyipqiIbNPUSD4uX go/E90PGTcwOpqquAa/xYv5NEhhXH50TQezdqufKKynHXfoJPv2PDUhwE w==; X-IronPort-AV: E=McAfee;i="6500,9779,10607"; a="414289042" X-IronPort-AV: E=Sophos;i="5.97,263,1669104000"; d="scan'208";a="414289042" Received: from orsmga007.jf.intel.com ([10.7.209.58]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Feb 2023 00:00:12 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10607"; a="658226993" X-IronPort-AV: E=Sophos;i="5.97,263,1669104000"; d="scan'208";a="658226993" Received: from ena1.iind.intel.com ([10.190.200.195]) by orsmga007.jf.intel.com with ESMTP; 01 Feb 2023 00:00:10 -0800 From: Harshad Narayane To: dev@dpdk.org Cc: cristian.dumitrescu@intel.com, harshad.suresh.narayane@intel.com, kamalakannan.r@intel.com Subject: [PATCH] pipeline: increase the pipeline instruction table size Date: Wed, 1 Feb 2023 07:58:57 +0000 Message-Id: <20230201075857.602848-1-harshad.suresh.narayane@intel.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org The complex P4 programs requires more custom instructions, therefore we increase the pipeline instruction table size from 256 to 1024. Signed-off-by: Harshad Narayane Signed-off-by: Kamalakannan R Acked-by: Cristian Dumitrescu --- lib/pipeline/rte_swx_pipeline_internal.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/lib/pipeline/rte_swx_pipeline_internal.h b/lib/pipeline/rte_swx_pipeline_internal.h index 335506039b..345b32502c 100644 --- a/lib/pipeline/rte_swx_pipeline_internal.h +++ b/lib/pipeline/rte_swx_pipeline_internal.h @@ -1465,7 +1465,7 @@ instr_operand_nbo(struct thread *t, const struct instr_operand *x) #endif #ifndef RTE_SWX_PIPELINE_INSTRUCTION_TABLE_SIZE_MAX -#define RTE_SWX_PIPELINE_INSTRUCTION_TABLE_SIZE_MAX 256 +#define RTE_SWX_PIPELINE_INSTRUCTION_TABLE_SIZE_MAX 1024 #endif struct rte_swx_pipeline {