From patchwork Wed Feb 1 07:30:13 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simei Su X-Patchwork-Id: 122796 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id EEED041B9B; Wed, 1 Feb 2023 08:31:11 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 82AAD42D0D; Wed, 1 Feb 2023 08:31:06 +0100 (CET) Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by mails.dpdk.org (Postfix) with ESMTP id 09AC14021F for ; Wed, 1 Feb 2023 08:31:03 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1675236664; x=1706772664; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=BRV5X1GQJlTCkguZ3bHWCqBwnHvKdur1TU9ikBLcKz0=; b=dqaue22yL+P5RYxY+cwgk7fwG+OCbscPQy0psid5PmA8Sap5kIpU9aJQ sJNDuWbQOOdIK7YR8Q6eM5GdkNujboRslILM8IyXTYbp5Jn+8C9wjp34Q i3ajZ7TDE4p2gIahLqbHhuGKEZzETRENyd8/EP8na5MWVUmwxX+aX5JPi 3a6PwZbvOXOb7XEevb8GPI1isQ3WwzVwCRw60Z4se6wd9t/ChOPVjFZ9R peet1ukcGQpbPTAmPsbZ6yY3z6VivxgaZOlOnb5j0kSKvqtfua+f9ZP2M 9OqO24ha7JlUe95WGKa2I4Jza+bcDpJoJbzc7sYk0BRMNlJX+rSQ25N4h Q==; X-IronPort-AV: E=McAfee;i="6500,9779,10607"; a="307733604" X-IronPort-AV: E=Sophos;i="5.97,263,1669104000"; d="scan'208";a="307733604" Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 31 Jan 2023 23:31:03 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10607"; a="993597237" X-IronPort-AV: E=Sophos;i="5.97,263,1669104000"; d="scan'208";a="993597237" Received: from unknown (HELO npg-dpdk-simeisu-cvl-119d218.sh.intel.com) ([10.67.119.208]) by fmsmga005.fm.intel.com with ESMTP; 31 Jan 2023 23:31:02 -0800 From: Simei Su To: qi.z.zhang@intel.com, junfeng.guo@intel.com Cc: dev@dpdk.org, wenjun1.wu@intel.com, Simei Su Subject: [PATCH v2 1/2] net/igc/base: expose packet pacing registers Date: Wed, 1 Feb 2023 15:30:13 +0800 Message-Id: <20230201073014.431924-2-simei.su@intel.com> X-Mailer: git-send-email 2.9.5 In-Reply-To: <20230201073014.431924-1-simei.su@intel.com> References: <20221220034741.447037-1-simei.su@intel.com> <20230201073014.431924-1-simei.su@intel.com> X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Add definitions for packet pacing(launch time offloading) related registers. Signed-off-by: Simei Su --- drivers/net/igc/base/igc_defines.h | 9 +++++++++ drivers/net/igc/base/igc_regs.h | 8 ++++++++ 2 files changed, 17 insertions(+) diff --git a/drivers/net/igc/base/igc_defines.h b/drivers/net/igc/base/igc_defines.h index dd7330a..280570b 100644 --- a/drivers/net/igc/base/igc_defines.h +++ b/drivers/net/igc/base/igc_defines.h @@ -188,6 +188,15 @@ #define IGC_RCTL_BSEX 0x02000000 /* Buffer size extension */ #define IGC_RCTL_SECRC 0x04000000 /* Strip Ethernet CRC */ +#define IGC_DTXMXPKTSZ_TSN 0x19 /* 1600 bytes of max TX DMA packet size */ +#define IGC_TXPBSIZE_TSN 0x04145145 /* 5k bytes buffer for each queue */ + +/* Transmit Scheduling */ +#define IGC_TQAVCTRL_TRANSMIT_MODE_TSN 0x00000001 +#define IGC_TQAVCTRL_ENHANCED_QAV 0x00000008 + +#define IGC_TXQCTL_QUEUE_MODE_LAUNCHT 0x00000001 + /* Use byte values for the following shift parameters * Usage: * psrctl |= (((ROUNDUP(value0, 128) >> IGC_PSRCTL_BSIZE0_SHIFT) & diff --git a/drivers/net/igc/base/igc_regs.h b/drivers/net/igc/base/igc_regs.h index d424387..e423814 100644 --- a/drivers/net/igc/base/igc_regs.h +++ b/drivers/net/igc/base/igc_regs.h @@ -602,6 +602,14 @@ #define IGC_RXMTRL 0x0B634 /* Time sync Rx EtherType and Msg Type - RW */ #define IGC_RXUDP 0x0B638 /* Time Sync Rx UDP Port - RW */ +#define IGC_QBVCYCLET 0x331C +#define IGC_QBVCYCLET_S 0x3320 +#define IGC_STQT(_n) (0x3324 + 0x4 * (_n)) +#define IGC_ENDQT(_n) (0x3334 + 0x4 * (_n)) +#define IGC_TXQCTL(_n) (0x3344 + 0x4 * (_n)) +#define IGC_BASET_L 0x3314 +#define IGC_BASET_H 0x3318 + /* Filtering Registers */ #define IGC_SAQF(_n) (0x05980 + (4 * (_n))) /* Source Address Queue Fltr */ #define IGC_DAQF(_n) (0x059A0 + (4 * (_n))) /* Dest Address Queue Fltr */