From patchwork Wed Jan 18 07:31:48 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Liu, Mingxia" X-Patchwork-Id: 122265 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 7A5F64240B; Wed, 18 Jan 2023 09:29:07 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id ED90942D5D; Wed, 18 Jan 2023 09:28:08 +0100 (CET) Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by mails.dpdk.org (Postfix) with ESMTP id 5799242D82 for ; Wed, 18 Jan 2023 09:28:04 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1674030484; x=1705566484; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=6cYwg6++whNf8ZLA+CkeVcg3UxpqqR8QRMZB4BBC1aM=; b=IhNI5A9BJ5GzzWdGahKsWrJVKB66QBfUgDC3w8djXdTiypq2hrpoJL2Z 5s6b8AqB5NhIHd+rH8e49s9NoMneaN/rYxMval679sgkDI0nwoYinuigr R5GWnpy/f9Pm5vcFgdLRUeDTBGDPKhI71YHn8Ia3wEQArvx49cc+fOGFB FFJ/VvCkLGHzHMaeAhzCD0wYz/FlwtqlJGjUQhxQ2tZS03LHTHc3Obwkg ZjuzwFEOn5Pe18UDVBFpBdNBhBbw1yAeVoMpALEAGwDyrzYVedlH4dwSq GY89JI3gAfuaaC3EpXvRi5lyROJejhxMgWWcV95gZrihPKJ2p1ATooER3 Q==; X-IronPort-AV: E=McAfee;i="6500,9779,10593"; a="305304294" X-IronPort-AV: E=Sophos;i="5.97,224,1669104000"; d="scan'208";a="305304294" Received: from orsmga007.jf.intel.com ([10.7.209.58]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Jan 2023 00:28:03 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10593"; a="652835341" X-IronPort-AV: E=Sophos;i="5.97,224,1669104000"; d="scan'208";a="652835341" Received: from dpdk-mingxial-01.sh.intel.com ([10.67.119.167]) by orsmga007.jf.intel.com with ESMTP; 18 Jan 2023 00:28:01 -0800 From: Mingxia Liu To: dev@dpdk.org, qi.z.zhang@intel.com, jingjing.wu@intel.com, beilei.xing@intel.com Cc: wenjun1.wu@intel.com, Mingxia Liu Subject: [PATCH v3 12/21] net/cpfl: support RSS Date: Wed, 18 Jan 2023 07:31:48 +0000 Message-Id: <20230118073154.903012-13-mingxia.liu@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230118073154.903012-1-mingxia.liu@intel.com> References: <20230113081931.221576-1-mingxia.liu@intel.com> <20230118073154.903012-1-mingxia.liu@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Add RSS support. Signed-off-by: Mingxia Liu --- drivers/net/cpfl/cpfl_ethdev.c | 51 ++++++++++++++++++++++++++++++++++ drivers/net/cpfl/cpfl_ethdev.h | 15 ++++++++++ 2 files changed, 66 insertions(+) diff --git a/drivers/net/cpfl/cpfl_ethdev.c b/drivers/net/cpfl/cpfl_ethdev.c index c678fe0354..49b8861df0 100644 --- a/drivers/net/cpfl/cpfl_ethdev.c +++ b/drivers/net/cpfl/cpfl_ethdev.c @@ -97,6 +97,8 @@ cpfl_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info) dev_info->max_mtu = vport->max_mtu; dev_info->min_mtu = RTE_ETHER_MIN_MTU; + dev_info->flow_type_rss_offloads = CPFL_RSS_OFFLOAD_ALL; + dev_info->tx_offload_capa = RTE_ETH_TX_OFFLOAD_MULTI_SEGS; dev_info->default_txconf = (struct rte_eth_txconf) { @@ -162,11 +164,49 @@ cpfl_dev_supported_ptypes_get(struct rte_eth_dev *dev __rte_unused) return ptypes; } +static int +cpfl_init_rss(struct idpf_vport *vport) +{ + struct rte_eth_rss_conf *rss_conf; + struct rte_eth_dev_data *dev_data; + uint16_t i, nb_q; + int ret = 0; + + dev_data = vport->dev_data; + rss_conf = &dev_data->dev_conf.rx_adv_conf.rss_conf; + nb_q = dev_data->nb_rx_queues; + + if (rss_conf->rss_key == NULL) { + for (i = 0; i < vport->rss_key_size; i++) + vport->rss_key[i] = (uint8_t)rte_rand(); + } else if (rss_conf->rss_key_len != vport->rss_key_size) { + PMD_INIT_LOG(ERR, "Invalid RSS key length in RSS configuration, should be %d", + vport->rss_key_size); + return -EINVAL; + } else { + rte_memcpy(vport->rss_key, rss_conf->rss_key, + vport->rss_key_size); + } + + for (i = 0; i < vport->rss_lut_size; i++) + vport->rss_lut[i] = i % nb_q; + + vport->rss_hf = IDPF_DEFAULT_RSS_HASH_EXPANDED; + + ret = idpf_config_rss(vport); + if (ret != 0) + PMD_INIT_LOG(ERR, "Failed to configure RSS"); + + return ret; +} + static int cpfl_dev_configure(struct rte_eth_dev *dev) { struct idpf_vport *vport = dev->data->dev_private; struct rte_eth_conf *conf = &dev->data->dev_conf; + struct idpf_adapter *adapter = vport->adapter; + int ret; if (conf->link_speeds & RTE_ETH_LINK_SPEED_FIXED) { PMD_INIT_LOG(ERR, "Setting link speed is not supported"); @@ -205,6 +245,17 @@ cpfl_dev_configure(struct rte_eth_dev *dev) return -ENOTSUP; } + if (adapter->caps.rss_caps != 0 && dev->data->nb_rx_queues != 0) { + ret = cpfl_init_rss(vport); + if (ret != 0) { + PMD_INIT_LOG(ERR, "Failed to init rss"); + return ret; + } + } else { + PMD_INIT_LOG(ERR, "RSS is not supported."); + return -1; + } + vport->max_pkt_len = (dev->data->mtu == 0) ? CPFL_DEFAULT_MTU : dev->data->mtu + CPFL_ETH_OVERHEAD; diff --git a/drivers/net/cpfl/cpfl_ethdev.h b/drivers/net/cpfl/cpfl_ethdev.h index 9ae543c2ad..0d60ee3aed 100644 --- a/drivers/net/cpfl/cpfl_ethdev.h +++ b/drivers/net/cpfl/cpfl_ethdev.h @@ -36,6 +36,21 @@ #define CPFL_ETH_OVERHEAD \ (RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN + CPFL_VLAN_TAG_SIZE * 2) +#define CPFL_RSS_OFFLOAD_ALL ( \ + RTE_ETH_RSS_IPV4 | \ + RTE_ETH_RSS_FRAG_IPV4 | \ + RTE_ETH_RSS_NONFRAG_IPV4_TCP | \ + RTE_ETH_RSS_NONFRAG_IPV4_UDP | \ + RTE_ETH_RSS_NONFRAG_IPV4_SCTP | \ + RTE_ETH_RSS_NONFRAG_IPV4_OTHER | \ + RTE_ETH_RSS_IPV6 | \ + RTE_ETH_RSS_FRAG_IPV6 | \ + RTE_ETH_RSS_NONFRAG_IPV6_TCP | \ + RTE_ETH_RSS_NONFRAG_IPV6_UDP | \ + RTE_ETH_RSS_NONFRAG_IPV6_SCTP | \ + RTE_ETH_RSS_NONFRAG_IPV6_OTHER | \ + RTE_ETH_RSS_L2_PAYLOAD) + #define CPFL_ADAPTER_NAME_LEN (PCI_PRI_STR_SIZE + 1) #define CPFL_ALARM_INTERVAL 50000 /* us */