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([10.233.181.123]) by fmsmga002.fm.intel.com with ESMTP; 17 Jan 2023 14:40:05 -0800 From: Nicolas Chautru To: dev@dpdk.org, maxime.coquelin@redhat.com Cc: hernan.vargas@intel.com, Nicolas Chautru Subject: [PATCH v1 3/6] baseband/acc: adding prefix to VRB1 registers Date: Tue, 17 Jan 2023 22:36:39 +0000 Message-Id: <20230117223642.17618-4-nicolas.chautru@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230117223642.17618-1-nicolas.chautru@intel.com> References: <20230117223642.17618-1-nicolas.chautru@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Adding prefix to register names specific to VRB1 (ACC200) to avoid future enum collision. Signed-off-by: Nicolas Chautru Reviewed-by: Maxime Coquelin --- drivers/baseband/acc/acc200_pf_enum.h | 174 +++++++++++++------------- drivers/baseband/acc/acc200_vf_enum.h | 128 +++++++++---------- drivers/baseband/acc/rte_vrb_pmd.c | 136 ++++++++++---------- drivers/baseband/acc/vrb_pmd.h | 134 ++++++++++---------- 4 files changed, 285 insertions(+), 287 deletions(-) diff --git a/drivers/baseband/acc/acc200_pf_enum.h b/drivers/baseband/acc/acc200_pf_enum.h index be1f8dcc8e..fc38465705 100644 --- a/drivers/baseband/acc/acc200_pf_enum.h +++ b/drivers/baseband/acc/acc200_pf_enum.h @@ -12,97 +12,97 @@ * Variable names are as is */ enum { - HWPfQmgrEgressQueuesTemplate = 0x0007FC00, - HWPfQmgrIngressAq = 0x00080000, - HWPfQmgrDepthLog2Grp = 0x00A00200, - HWPfQmgrTholdGrp = 0x00A00300, - HWPfQmgrGrpTmplateReg0Indx = 0x00A00600, - HWPfQmgrGrpTmplateReg1Indx = 0x00A00700, - HWPfQmgrGrpTmplateReg2indx = 0x00A00800, - HWPfQmgrGrpTmplateReg3Indx = 0x00A00900, - HWPfQmgrGrpTmplateReg4Indx = 0x00A00A00, - HWPfQmgrVfBaseAddr = 0x00A01000, - HWPfQmgrArbQDepthGrp = 0x00A02F00, - HWPfQmgrGrpFunction0 = 0x00A02F40, - HWPfQmgrGrpFunction1 = 0x00A02F44, - HWPfQmgrGrpPriority = 0x00A02F48, - HWPfQmgrAqEnableVf = 0x00A10000, - HWPfQmgrRingSizeVf = 0x00A20004, - HWPfQmgrGrpDepthLog20Vf = 0x00A20008, - HWPfQmgrGrpDepthLog21Vf = 0x00A2000C, - HWPfFabricM2iBufferReg = 0x00B30000, - HWPfFabricI2Mdma_weight = 0x00B31044, - HwPfFecUl5gIbDebugReg = 0x00B40200, - HWPfFftConfig0 = 0x00B58004, - HWPfFftRamPageAccess = 0x00B5800C, - HWPfFftRamOff = 0x00B58800, - HWPfDmaConfig0Reg = 0x00B80000, - HWPfDmaConfig1Reg = 0x00B80004, - HWPfDmaQmgrAddrReg = 0x00B80008, - HWPfDmaAxcacheReg = 0x00B80010, - HWPfDmaAxiControl = 0x00B8002C, - HWPfDmaQmanen = 0x00B80040, - HWPfDma4gdlIbThld = 0x00B800CC, - HWPfDmaCfgRrespBresp = 0x00B80814, - HWPfDmaDescriptorSignatuture = 0x00B80868, - HWPfDmaErrorDetectionEn = 0x00B80870, - HWPfDmaFec5GulDescBaseLoRegVf = 0x00B88020, - HWPfDmaFec5GulDescBaseHiRegVf = 0x00B88024, - HWPfDmaFec5GulRespPtrLoRegVf = 0x00B88028, - HWPfDmaFec5GulRespPtrHiRegVf = 0x00B8802C, - HWPfDmaFec5GdlDescBaseLoRegVf = 0x00B88040, - HWPfDmaFec5GdlDescBaseHiRegVf = 0x00B88044, - HWPfDmaFec5GdlRespPtrLoRegVf = 0x00B88048, - HWPfDmaFec5GdlRespPtrHiRegVf = 0x00B8804C, - HWPfDmaFec4GulDescBaseLoRegVf = 0x00B88060, - HWPfDmaFec4GulDescBaseHiRegVf = 0x00B88064, - HWPfDmaFec4GulRespPtrLoRegVf = 0x00B88068, - HWPfDmaFec4GulRespPtrHiRegVf = 0x00B8806C, - HWPfDmaFec4GdlDescBaseLoRegVf = 0x00B88080, - HWPfDmaFec4GdlDescBaseHiRegVf = 0x00B88084, - HWPfDmaFec4GdlRespPtrLoRegVf = 0x00B88088, - HWPfDmaFec4GdlRespPtrHiRegVf = 0x00B8808C, - HWPfDmaFftDescBaseLoRegVf = 0x00B880A0, - HWPfDmaFftDescBaseHiRegVf = 0x00B880A4, - HWPfDmaFftRespPtrLoRegVf = 0x00B880A8, - HWPfDmaFftRespPtrHiRegVf = 0x00B880AC, - HWPfQosmonAEvalOverflow0 = 0x00B90008, - HWPfPermonACntrlRegVf = 0x00B98000, - HWPfQosmonBEvalOverflow0 = 0x00BA0008, - HWPfPermonBCntrlRegVf = 0x00BA8000, - HWPfPermonCCntrlRegVf = 0x00BB8000, - HWPfHiInfoRingBaseLoRegPf = 0x00C84014, - HWPfHiInfoRingBaseHiRegPf = 0x00C84018, - HWPfHiInfoRingPointerRegPf = 0x00C8401C, - HWPfHiInfoRingIntWrEnRegPf = 0x00C84020, - HWPfHiBlockTransmitOnErrorEn = 0x00C84038, - HWPfHiCfgMsiIntWrEnRegPf = 0x00C84040, - HWPfHiMsixVectorMapperPf = 0x00C84060, - HWPfHiPfMode = 0x00C84108, - HWPfHiClkGateHystReg = 0x00C8410C, - HWPfHiMsiDropEnableReg = 0x00C84114, - HWPfHiSectionPowerGatingReq = 0x00C84128, - HWPfHiSectionPowerGatingAck = 0x00C8412C, + VRB1_PfQmgrEgressQueuesTemplate = 0x0007FC00, + VRB1_PfQmgrIngressAq = 0x00080000, + VRB1_PfQmgrDepthLog2Grp = 0x00A00200, + VRB1_PfQmgrTholdGrp = 0x00A00300, + VRB1_PfQmgrGrpTmplateReg0Indx = 0x00A00600, + VRB1_PfQmgrGrpTmplateReg1Indx = 0x00A00700, + VRB1_PfQmgrGrpTmplateReg2indx = 0x00A00800, + VRB1_PfQmgrGrpTmplateReg3Indx = 0x00A00900, + VRB1_PfQmgrGrpTmplateReg4Indx = 0x00A00A00, + VRB1_PfQmgrVfBaseAddr = 0x00A01000, + VRB1_PfQmgrArbQDepthGrp = 0x00A02F00, + VRB1_PfQmgrGrpFunction0 = 0x00A02F40, + VRB1_PfQmgrGrpFunction1 = 0x00A02F44, + VRB1_PfQmgrGrpPriority = 0x00A02F48, + VRB1_PfQmgrAqEnableVf = 0x00A10000, + VRB1_PfQmgrRingSizeVf = 0x00A20004, + VRB1_PfQmgrGrpDepthLog20Vf = 0x00A20008, + VRB1_PfQmgrGrpDepthLog21Vf = 0x00A2000C, + VRB1_PfFabricM2iBufferReg = 0x00B30000, + VRB1_PfFabricI2Mdma_weight = 0x00B31044, + VRB1_PfFecUl5gIbDebugReg = 0x00B40200, + VRB1_PfFftConfig0 = 0x00B58004, + VRB1_PfFftRamPageAccess = 0x00B5800C, + VRB1_PfFftRamOff = 0x00B58800, + VRB1_PfDmaConfig0Reg = 0x00B80000, + VRB1_PfDmaConfig1Reg = 0x00B80004, + VRB1_PfDmaQmgrAddrReg = 0x00B80008, + VRB1_PfDmaAxcacheReg = 0x00B80010, + VRB1_PfDmaAxiControl = 0x00B8002C, + VRB1_PfDmaQmanen = 0x00B80040, + VRB1_PfDma4gdlIbThld = 0x00B800CC, + VRB1_PfDmaCfgRrespBresp = 0x00B80814, + VRB1_PfDmaDescriptorSignatuture = 0x00B80868, + VRB1_PfDmaErrorDetectionEn = 0x00B80870, + VRB1_PfDmaFec5GulDescBaseLoRegVf = 0x00B88020, + VRB1_PfDmaFec5GulDescBaseHiRegVf = 0x00B88024, + VRB1_PfDmaFec5GulRespPtrLoRegVf = 0x00B88028, + VRB1_PfDmaFec5GulRespPtrHiRegVf = 0x00B8802C, + VRB1_PfDmaFec5GdlDescBaseLoRegVf = 0x00B88040, + VRB1_PfDmaFec5GdlDescBaseHiRegVf = 0x00B88044, + VRB1_PfDmaFec5GdlRespPtrLoRegVf = 0x00B88048, + VRB1_PfDmaFec5GdlRespPtrHiRegVf = 0x00B8804C, + VRB1_PfDmaFec4GulDescBaseLoRegVf = 0x00B88060, + VRB1_PfDmaFec4GulDescBaseHiRegVf = 0x00B88064, + VRB1_PfDmaFec4GulRespPtrLoRegVf = 0x00B88068, + VRB1_PfDmaFec4GulRespPtrHiRegVf = 0x00B8806C, + VRB1_PfDmaFec4GdlDescBaseLoRegVf = 0x00B88080, + VRB1_PfDmaFec4GdlDescBaseHiRegVf = 0x00B88084, + VRB1_PfDmaFec4GdlRespPtrLoRegVf = 0x00B88088, + VRB1_PfDmaFec4GdlRespPtrHiRegVf = 0x00B8808C, + VRB1_PfDmaFftDescBaseLoRegVf = 0x00B880A0, + VRB1_PfDmaFftDescBaseHiRegVf = 0x00B880A4, + VRB1_PfDmaFftRespPtrLoRegVf = 0x00B880A8, + VRB1_PfDmaFftRespPtrHiRegVf = 0x00B880AC, + VRB1_PfQosmonAEvalOverflow0 = 0x00B90008, + VRB1_PfPermonACntrlRegVf = 0x00B98000, + VRB1_PfQosmonBEvalOverflow0 = 0x00BA0008, + VRB1_PfPermonBCntrlRegVf = 0x00BA8000, + VRB1_PfPermonCCntrlRegVf = 0x00BB8000, + VRB1_PfHiInfoRingBaseLoRegPf = 0x00C84014, + VRB1_PfHiInfoRingBaseHiRegPf = 0x00C84018, + VRB1_PfHiInfoRingPointerRegPf = 0x00C8401C, + VRB1_PfHiInfoRingIntWrEnRegPf = 0x00C84020, + VRB1_PfHiBlockTransmitOnErrorEn = 0x00C84038, + VRB1_PfHiCfgMsiIntWrEnRegPf = 0x00C84040, + VRB1_PfHiMsixVectorMapperPf = 0x00C84060, + VRB1_PfHiPfMode = 0x00C84108, + VRB1_PfHiClkGateHystReg = 0x00C8410C, + VRB1_PfHiMsiDropEnableReg = 0x00C84114, + VRB1_PfHiSectionPowerGatingReq = 0x00C84128, + VRB1_PfHiSectionPowerGatingAck = 0x00C8412C, }; /* TIP PF Interrupt numbers */ enum { - ACC200_PF_INT_QMGR_AQ_OVERFLOW = 0, - ACC200_PF_INT_DOORBELL_VF_2_PF = 1, - ACC200_PF_INT_ILLEGAL_FORMAT = 2, - ACC200_PF_INT_QMGR_DISABLED_ACCESS = 3, - ACC200_PF_INT_QMGR_AQ_OVERTHRESHOLD = 4, - ACC200_PF_INT_DMA_DL_DESC_IRQ = 5, - ACC200_PF_INT_DMA_UL_DESC_IRQ = 6, - ACC200_PF_INT_DMA_FFT_DESC_IRQ = 7, - ACC200_PF_INT_DMA_UL5G_DESC_IRQ = 8, - ACC200_PF_INT_DMA_DL5G_DESC_IRQ = 9, - ACC200_PF_INT_DMA_MLD_DESC_IRQ = 10, - ACC200_PF_INT_ARAM_ECC_1BIT_ERR = 11, - ACC200_PF_INT_PARITY_ERR = 12, - ACC200_PF_INT_QMGR_ERR = 13, - ACC200_PF_INT_INT_REQ_OVERFLOW = 14, - ACC200_PF_INT_APB_TIMEOUT = 15, + ACC_PF_INT_QMGR_AQ_OVERFLOW = 0, + ACC_PF_INT_DOORBELL_VF_2_PF = 1, + ACC_PF_INT_ILLEGAL_FORMAT = 2, + ACC_PF_INT_QMGR_DISABLED_ACCESS = 3, + ACC_PF_INT_QMGR_AQ_OVERTHRESHOLD = 4, + ACC_PF_INT_DMA_DL_DESC_IRQ = 5, + ACC_PF_INT_DMA_UL_DESC_IRQ = 6, + ACC_PF_INT_DMA_FFT_DESC_IRQ = 7, + ACC_PF_INT_DMA_UL5G_DESC_IRQ = 8, + ACC_PF_INT_DMA_DL5G_DESC_IRQ = 9, + ACC_PF_INT_DMA_MLD_DESC_IRQ = 10, + ACC_PF_INT_ARAM_ECC_1BIT_ERR = 11, + ACC_PF_INT_PARITY_ERR = 12, + ACC_PF_INT_QMGR_ERR = 13, + ACC_PF_INT_INT_REQ_OVERFLOW = 14, + ACC_PF_INT_APB_TIMEOUT = 15, }; #endif /* ACC200_PF_ENUM_H */ diff --git a/drivers/baseband/acc/acc200_vf_enum.h b/drivers/baseband/acc/acc200_vf_enum.h index 0d354208ab..62a4f369bc 100644 --- a/drivers/baseband/acc/acc200_vf_enum.h +++ b/drivers/baseband/acc/acc200_vf_enum.h @@ -10,74 +10,74 @@ * This is automatically generated from RDL, format may change with new RDL */ enum { - HWVfQmgrIngressAq = 0x00000000, - HWVfHiVfToPfDbellVf = 0x00000800, - HWVfHiPfToVfDbellVf = 0x00000808, - HWVfHiInfoRingBaseLoVf = 0x00000810, - HWVfHiInfoRingBaseHiVf = 0x00000814, - HWVfHiInfoRingPointerVf = 0x00000818, - HWVfHiInfoRingIntWrEnVf = 0x00000820, - HWVfHiInfoRingPf2VfWrEnVf = 0x00000824, - HWVfHiMsixVectorMapperVf = 0x00000860, - HWVfDmaFec5GulDescBaseLoRegVf = 0x00000920, - HWVfDmaFec5GulDescBaseHiRegVf = 0x00000924, - HWVfDmaFec5GulRespPtrLoRegVf = 0x00000928, - HWVfDmaFec5GulRespPtrHiRegVf = 0x0000092C, - HWVfDmaFec5GdlDescBaseLoRegVf = 0x00000940, - HWVfDmaFec5GdlDescBaseHiRegVf = 0x00000944, - HWVfDmaFec5GdlRespPtrLoRegVf = 0x00000948, - HWVfDmaFec5GdlRespPtrHiRegVf = 0x0000094C, - HWVfDmaFec4GulDescBaseLoRegVf = 0x00000960, - HWVfDmaFec4GulDescBaseHiRegVf = 0x00000964, - HWVfDmaFec4GulRespPtrLoRegVf = 0x00000968, - HWVfDmaFec4GulRespPtrHiRegVf = 0x0000096C, - HWVfDmaFec4GdlDescBaseLoRegVf = 0x00000980, - HWVfDmaFec4GdlDescBaseHiRegVf = 0x00000984, - HWVfDmaFec4GdlRespPtrLoRegVf = 0x00000988, - HWVfDmaFec4GdlRespPtrHiRegVf = 0x0000098C, - HWVfDmaFftDescBaseLoRegVf = 0x000009A0, - HWVfDmaFftDescBaseHiRegVf = 0x000009A4, - HWVfDmaFftRespPtrLoRegVf = 0x000009A8, - HWVfDmaFftRespPtrHiRegVf = 0x000009AC, - HWVfQmgrAqResetVf = 0x00000E00, - HWVfQmgrRingSizeVf = 0x00000E04, - HWVfQmgrGrpDepthLog20Vf = 0x00000E08, - HWVfQmgrGrpDepthLog21Vf = 0x00000E0C, - HWVfQmgrGrpFunction0Vf = 0x00000E10, - HWVfQmgrGrpFunction1Vf = 0x00000E14, - HWVfPmACntrlRegVf = 0x00000F40, - HWVfPmACountVf = 0x00000F48, - HWVfPmAKCntLoVf = 0x00000F50, - HWVfPmAKCntHiVf = 0x00000F54, - HWVfPmADeltaCntLoVf = 0x00000F60, - HWVfPmADeltaCntHiVf = 0x00000F64, - HWVfPmBCntrlRegVf = 0x00000F80, - HWVfPmBCountVf = 0x00000F88, - HWVfPmBKCntLoVf = 0x00000F90, - HWVfPmBKCntHiVf = 0x00000F94, - HWVfPmBDeltaCntLoVf = 0x00000FA0, - HWVfPmBDeltaCntHiVf = 0x00000FA4, - HWVfPmCCntrlRegVf = 0x00000FC0, - HWVfPmCCountVf = 0x00000FC8, - HWVfPmCKCntLoVf = 0x00000FD0, - HWVfPmCKCntHiVf = 0x00000FD4, - HWVfPmCDeltaCntLoVf = 0x00000FE0, - HWVfPmCDeltaCntHiVf = 0x00000FE4 + VRB1_VfQmgrIngressAq = 0x00000000, + VRB1_VfHiVfToPfDbellVf = 0x00000800, + VRB1_VfHiPfToVfDbellVf = 0x00000808, + VRB1_VfHiInfoRingBaseLoVf = 0x00000810, + VRB1_VfHiInfoRingBaseHiVf = 0x00000814, + VRB1_VfHiInfoRingPointerVf = 0x00000818, + VRB1_VfHiInfoRingIntWrEnVf = 0x00000820, + VRB1_VfHiInfoRingPf2VfWrEnVf = 0x00000824, + VRB1_VfHiMsixVectorMapperVf = 0x00000860, + VRB1_VfDmaFec5GulDescBaseLoRegVf = 0x00000920, + VRB1_VfDmaFec5GulDescBaseHiRegVf = 0x00000924, + VRB1_VfDmaFec5GulRespPtrLoRegVf = 0x00000928, + VRB1_VfDmaFec5GulRespPtrHiRegVf = 0x0000092C, + VRB1_VfDmaFec5GdlDescBaseLoRegVf = 0x00000940, + VRB1_VfDmaFec5GdlDescBaseHiRegVf = 0x00000944, + VRB1_VfDmaFec5GdlRespPtrLoRegVf = 0x00000948, + VRB1_VfDmaFec5GdlRespPtrHiRegVf = 0x0000094C, + VRB1_VfDmaFec4GulDescBaseLoRegVf = 0x00000960, + VRB1_VfDmaFec4GulDescBaseHiRegVf = 0x00000964, + VRB1_VfDmaFec4GulRespPtrLoRegVf = 0x00000968, + VRB1_VfDmaFec4GulRespPtrHiRegVf = 0x0000096C, + VRB1_VfDmaFec4GdlDescBaseLoRegVf = 0x00000980, + VRB1_VfDmaFec4GdlDescBaseHiRegVf = 0x00000984, + VRB1_VfDmaFec4GdlRespPtrLoRegVf = 0x00000988, + VRB1_VfDmaFec4GdlRespPtrHiRegVf = 0x0000098C, + VRB1_VfDmaFftDescBaseLoRegVf = 0x000009A0, + VRB1_VfDmaFftDescBaseHiRegVf = 0x000009A4, + VRB1_VfDmaFftRespPtrLoRegVf = 0x000009A8, + VRB1_VfDmaFftRespPtrHiRegVf = 0x000009AC, + VRB1_VfQmgrAqResetVf = 0x00000E00, + VRB1_VfQmgrRingSizeVf = 0x00000E04, + VRB1_VfQmgrGrpDepthLog20Vf = 0x00000E08, + VRB1_VfQmgrGrpDepthLog21Vf = 0x00000E0C, + VRB1_VfQmgrGrpFunction0Vf = 0x00000E10, + VRB1_VfQmgrGrpFunction1Vf = 0x00000E14, + VRB1_VfPmACntrlRegVf = 0x00000F40, + VRB1_VfPmACountVf = 0x00000F48, + VRB1_VfPmAKCntLoVf = 0x00000F50, + VRB1_VfPmAKCntHiVf = 0x00000F54, + VRB1_VfPmADeltaCntLoVf = 0x00000F60, + VRB1_VfPmADeltaCntHiVf = 0x00000F64, + VRB1_VfPmBCntrlRegVf = 0x00000F80, + VRB1_VfPmBCountVf = 0x00000F88, + VRB1_VfPmBKCntLoVf = 0x00000F90, + VRB1_VfPmBKCntHiVf = 0x00000F94, + VRB1_VfPmBDeltaCntLoVf = 0x00000FA0, + VRB1_VfPmBDeltaCntHiVf = 0x00000FA4, + VRB1_VfPmCCntrlRegVf = 0x00000FC0, + VRB1_VfPmCCountVf = 0x00000FC8, + VRB1_VfPmCKCntLoVf = 0x00000FD0, + VRB1_VfPmCKCntHiVf = 0x00000FD4, + VRB1_VfPmCDeltaCntLoVf = 0x00000FE0, + VRB1_VfPmCDeltaCntHiVf = 0x00000FE4 }; /* TIP VF Interrupt numbers */ enum { - ACC200_VF_INT_QMGR_AQ_OVERFLOW = 0, - ACC200_VF_INT_DOORBELL_PF_2_VF = 1, - ACC200_VF_INT_ILLEGAL_FORMAT = 2, - ACC200_VF_INT_QMGR_DISABLED_ACCESS = 3, - ACC200_VF_INT_QMGR_AQ_OVERTHRESHOLD = 4, - ACC200_VF_INT_DMA_DL_DESC_IRQ = 5, - ACC200_VF_INT_DMA_UL_DESC_IRQ = 6, - ACC200_VF_INT_DMA_FFT_DESC_IRQ = 7, - ACC200_VF_INT_DMA_UL5G_DESC_IRQ = 8, - ACC200_VF_INT_DMA_DL5G_DESC_IRQ = 9, - ACC200_VF_INT_DMA_MLD_DESC_IRQ = 10, + ACC_VF_INT_QMGR_AQ_OVERFLOW = 0, + ACC_VF_INT_DOORBELL_PF_2_VF = 1, + ACC_VF_INT_ILLEGAL_FORMAT = 2, + ACC_VF_INT_QMGR_DISABLED_ACCESS = 3, + ACC_VF_INT_QMGR_AQ_OVERTHRESHOLD = 4, + ACC_VF_INT_DMA_DL_DESC_IRQ = 5, + ACC_VF_INT_DMA_UL_DESC_IRQ = 6, + ACC_VF_INT_DMA_FFT_DESC_IRQ = 7, + ACC_VF_INT_DMA_UL5G_DESC_IRQ = 8, + ACC_VF_INT_DMA_DL5G_DESC_IRQ = 9, + ACC_VF_INT_DMA_MLD_DESC_IRQ = 10, }; #endif /* ACC200_VF_ENUM_H */ diff --git a/drivers/baseband/acc/rte_vrb_pmd.c b/drivers/baseband/acc/rte_vrb_pmd.c index 49cc3696a9..01e018f233 100644 --- a/drivers/baseband/acc/rte_vrb_pmd.c +++ b/drivers/baseband/acc/rte_vrb_pmd.c @@ -33,10 +33,10 @@ queue_offset(bool pf_device, uint8_t vf_id, uint8_t qgrp_id, uint16_t aq_id) { if (pf_device) return ((vf_id << 12) + (qgrp_id << 7) + (aq_id << 3) + - HWPfQmgrIngressAq); + VRB1_PfQmgrIngressAq); else return ((qgrp_id << 7) + (aq_id << 3) + - HWVfQmgrIngressAq); + VRB1_VfQmgrIngressAq); } enum {UL_4G = 0, UL_5G, DL_4G, DL_5G, FFT, NUM_ACC}; @@ -313,8 +313,8 @@ acc200_check_ir(struct acc_device *acc200_dev) ring_data = acc200_dev->info_ring + (acc200_dev->info_ring_head & ACC_INFO_RING_MASK); while (ring_data->valid) { - if ((ring_data->int_nb < ACC200_PF_INT_DMA_DL_DESC_IRQ) || ( - ring_data->int_nb > ACC200_PF_INT_DMA_DL5G_DESC_IRQ)) { + if ((ring_data->int_nb < ACC_PF_INT_DMA_DL_DESC_IRQ) || ( + ring_data->int_nb > ACC_PF_INT_DMA_DL5G_DESC_IRQ)) { rte_bbdev_log(WARNING, "InfoRing: ITR:%d Info:0x%x", ring_data->int_nb, ring_data->detailed_info); /* Initialize Info Ring entry and move forward. */ @@ -343,11 +343,11 @@ acc200_dev_interrupt_handler(void *cb_arg) ring_data->val, ring_data->int_nb); switch (ring_data->int_nb) { - case ACC200_PF_INT_DMA_DL_DESC_IRQ: - case ACC200_PF_INT_DMA_UL_DESC_IRQ: - case ACC200_PF_INT_DMA_FFT_DESC_IRQ: - case ACC200_PF_INT_DMA_UL5G_DESC_IRQ: - case ACC200_PF_INT_DMA_DL5G_DESC_IRQ: + case ACC_PF_INT_DMA_DL_DESC_IRQ: + case ACC_PF_INT_DMA_UL_DESC_IRQ: + case ACC_PF_INT_DMA_FFT_DESC_IRQ: + case ACC_PF_INT_DMA_UL5G_DESC_IRQ: + case ACC_PF_INT_DMA_DL5G_DESC_IRQ: deq_intr_det.queue_id = get_queue_id_from_ring_info( dev->data, *ring_data); if (deq_intr_det.queue_id == UINT16_MAX) { @@ -370,11 +370,11 @@ acc200_dev_interrupt_handler(void *cb_arg) "ACC200 VF Interrupt received, Info Ring data: 0x%x\n", ring_data->val); switch (ring_data->int_nb) { - case ACC200_VF_INT_DMA_DL_DESC_IRQ: - case ACC200_VF_INT_DMA_UL_DESC_IRQ: - case ACC200_VF_INT_DMA_FFT_DESC_IRQ: - case ACC200_VF_INT_DMA_UL5G_DESC_IRQ: - case ACC200_VF_INT_DMA_DL5G_DESC_IRQ: + case ACC_VF_INT_DMA_DL_DESC_IRQ: + case ACC_VF_INT_DMA_UL_DESC_IRQ: + case ACC_VF_INT_DMA_FFT_DESC_IRQ: + case ACC_VF_INT_DMA_UL5G_DESC_IRQ: + case ACC_VF_INT_DMA_DL5G_DESC_IRQ: /* VFs are not aware of their vf_id - it's set to 0. */ ring_data->vf_id = 0; deq_intr_det.queue_id = get_queue_id_from_ring_info( @@ -498,7 +498,7 @@ acc200_setup_queues(struct rte_bbdev *dev, uint16_t num_queues, int socket_id) /* Release AXI from PF. */ if (d->pf_device) - acc_reg_write(d, HWPfDmaAxiControl, 1); + acc_reg_write(d, VRB1_PfDmaAxiControl, 1); acc_reg_write(d, d->reg_addr->dma_ring_ul5g_hi, phys_high); acc_reg_write(d, d->reg_addr->dma_ring_ul5g_lo, phys_low); @@ -3423,7 +3423,7 @@ acc200_configure(const char *dev_name, struct rte_acc_conf *conf) rte_memcpy(&d->acc_conf, conf, sizeof(d->acc_conf)); /* Check we are already out of PG. */ - status = acc_reg_read(d, HWPfHiSectionPowerGatingAck); + status = acc_reg_read(d, VRB1_PfHiSectionPowerGatingAck); if (status > 0) { if (status != ACC200_PG_MASK_0) { rte_bbdev_log(ERR, "Unexpected status %x %x", @@ -3431,69 +3431,69 @@ acc200_configure(const char *dev_name, struct rte_acc_conf *conf) return -ENODEV; } /* Clock gate sections that will be un-PG. */ - acc_reg_write(d, HWPfHiClkGateHystReg, ACC200_CLK_DIS); + acc_reg_write(d, VRB1_PfHiClkGateHystReg, ACC200_CLK_DIS); /* Un-PG required sections. */ - acc_reg_write(d, HWPfHiSectionPowerGatingReq, + acc_reg_write(d, VRB1_PfHiSectionPowerGatingReq, ACC200_PG_MASK_1); - status = acc_reg_read(d, HWPfHiSectionPowerGatingAck); + status = acc_reg_read(d, VRB1_PfHiSectionPowerGatingAck); if (status != ACC200_PG_MASK_1) { rte_bbdev_log(ERR, "Unexpected status %x %x", status, ACC200_PG_MASK_1); return -ENODEV; } - acc_reg_write(d, HWPfHiSectionPowerGatingReq, + acc_reg_write(d, VRB1_PfHiSectionPowerGatingReq, ACC200_PG_MASK_2); - status = acc_reg_read(d, HWPfHiSectionPowerGatingAck); + status = acc_reg_read(d, VRB1_PfHiSectionPowerGatingAck); if (status != ACC200_PG_MASK_2) { rte_bbdev_log(ERR, "Unexpected status %x %x", status, ACC200_PG_MASK_2); return -ENODEV; } - acc_reg_write(d, HWPfHiSectionPowerGatingReq, + acc_reg_write(d, VRB1_PfHiSectionPowerGatingReq, ACC200_PG_MASK_3); - status = acc_reg_read(d, HWPfHiSectionPowerGatingAck); + status = acc_reg_read(d, VRB1_PfHiSectionPowerGatingAck); if (status != ACC200_PG_MASK_3) { rte_bbdev_log(ERR, "Unexpected status %x %x", status, ACC200_PG_MASK_3); return -ENODEV; } /* Enable clocks for all sections. */ - acc_reg_write(d, HWPfHiClkGateHystReg, ACC200_CLK_EN); + acc_reg_write(d, VRB1_PfHiClkGateHystReg, ACC200_CLK_EN); } /* Explicitly releasing AXI as this may be stopped after PF FLR/BME. */ - address = HWPfDmaAxiControl; + address = VRB1_PfDmaAxiControl; value = 1; acc_reg_write(d, address, value); /* Set the fabric mode. */ - address = HWPfFabricM2iBufferReg; + address = VRB1_PfFabricM2iBufferReg; value = ACC200_FABRIC_MODE; acc_reg_write(d, address, value); /* Set default descriptor signature. */ - address = HWPfDmaDescriptorSignatuture; + address = VRB1_PfDmaDescriptorSignatuture; value = 0; acc_reg_write(d, address, value); /* Enable the Error Detection in DMA. */ value = ACC200_CFG_DMA_ERROR; - address = HWPfDmaErrorDetectionEn; + address = VRB1_PfDmaErrorDetectionEn; acc_reg_write(d, address, value); /* AXI Cache configuration. */ value = ACC200_CFG_AXI_CACHE; - address = HWPfDmaAxcacheReg; + address = VRB1_PfDmaAxcacheReg; acc_reg_write(d, address, value); /* AXI Response configuration. */ - acc_reg_write(d, HWPfDmaCfgRrespBresp, 0x0); + acc_reg_write(d, VRB1_PfDmaCfgRrespBresp, 0x0); /* Default DMA Configuration (Qmgr Enabled). */ - address = HWPfDmaConfig0Reg; + address = VRB1_PfDmaConfig0Reg; value = 0; acc_reg_write(d, address, value); - address = HWPfDmaQmanen; + address = VRB1_PfDmaQmanen; value = 0; acc_reg_write(d, address, value); @@ -3501,18 +3501,18 @@ acc200_configure(const char *dev_name, struct rte_acc_conf *conf) rlim = 0; alen = 1; timestamp = 0; - address = HWPfDmaConfig1Reg; + address = VRB1_PfDmaConfig1Reg; value = (1 << 31) + (rlim << 8) + (timestamp << 6) + alen; acc_reg_write(d, address, value); /* Default FFT configuration. */ - address = HWPfFftConfig0; + address = VRB1_PfFftConfig0; value = ACC200_FFT_CFG_0; acc_reg_write(d, address, value); /* Configure DMA Qmanager addresses. */ - address = HWPfDmaQmgrAddrReg; - value = HWPfQmgrEgressQueuesTemplate; + address = VRB1_PfDmaQmgrAddrReg; + value = VRB1_PfQmgrEgressQueuesTemplate; acc_reg_write(d, address, value); /* ===== Qmgr Configuration ===== */ @@ -3523,12 +3523,10 @@ acc200_configure(const char *dev_name, struct rte_acc_conf *conf) conf->q_dl_5g.num_qgroups + conf->q_fft.num_qgroups; for (qg_idx = 0; qg_idx < ACC200_NUM_QGRPS; qg_idx++) { - address = HWPfQmgrDepthLog2Grp + - ACC_BYTES_IN_WORD * qg_idx; + address = VRB1_PfQmgrDepthLog2Grp + ACC_BYTES_IN_WORD * qg_idx; value = aqDepth(qg_idx, conf); acc_reg_write(d, address, value); - address = HWPfQmgrTholdGrp + - ACC_BYTES_IN_WORD * qg_idx; + address = VRB1_PfQmgrTholdGrp + ACC_BYTES_IN_WORD * qg_idx; value = (1 << 16) + (1 << (aqDepth(qg_idx, conf) - 1)); acc_reg_write(d, address, value); } @@ -3536,21 +3534,21 @@ acc200_configure(const char *dev_name, struct rte_acc_conf *conf) /* Template Priority in incremental order. */ for (template_idx = 0; template_idx < ACC_NUM_TMPL; template_idx++) { - address = HWPfQmgrGrpTmplateReg0Indx + ACC_BYTES_IN_WORD * template_idx; + address = VRB1_PfQmgrGrpTmplateReg0Indx + ACC_BYTES_IN_WORD * template_idx; value = ACC_TMPL_PRI_0; acc_reg_write(d, address, value); - address = HWPfQmgrGrpTmplateReg1Indx + ACC_BYTES_IN_WORD * template_idx; + address = VRB1_PfQmgrGrpTmplateReg1Indx + ACC_BYTES_IN_WORD * template_idx; value = ACC_TMPL_PRI_1; acc_reg_write(d, address, value); - address = HWPfQmgrGrpTmplateReg2indx + ACC_BYTES_IN_WORD * template_idx; + address = VRB1_PfQmgrGrpTmplateReg2indx + ACC_BYTES_IN_WORD * template_idx; value = ACC_TMPL_PRI_2; acc_reg_write(d, address, value); - address = HWPfQmgrGrpTmplateReg3Indx + ACC_BYTES_IN_WORD * template_idx; + address = VRB1_PfQmgrGrpTmplateReg3Indx + ACC_BYTES_IN_WORD * template_idx; value = ACC_TMPL_PRI_3; acc_reg_write(d, address, value); } - address = HWPfQmgrGrpPriority; + address = VRB1_PfQmgrGrpPriority; value = ACC200_CFG_QMGR_HI_P; acc_reg_write(d, address, value); @@ -3558,7 +3556,7 @@ acc200_configure(const char *dev_name, struct rte_acc_conf *conf) for (template_idx = 0; template_idx < ACC_NUM_TMPL; template_idx++) { value = 0; - address = HWPfQmgrGrpTmplateReg4Indx + address = VRB1_PfQmgrGrpTmplateReg4Indx + ACC_BYTES_IN_WORD * template_idx; acc_reg_write(d, address, value); } @@ -3571,7 +3569,7 @@ acc200_configure(const char *dev_name, struct rte_acc_conf *conf) for (template_idx = ACC200_SIG_UL_4G; template_idx <= ACC200_SIG_UL_4G_LAST; template_idx++) { - address = HWPfQmgrGrpTmplateReg4Indx + address = VRB1_PfQmgrGrpTmplateReg4Indx + ACC_BYTES_IN_WORD * template_idx; acc_reg_write(d, address, value); } @@ -3586,9 +3584,9 @@ acc200_configure(const char *dev_name, struct rte_acc_conf *conf) template_idx <= ACC200_SIG_UL_5G_LAST; template_idx++) { /* Check engine power-on status */ - address = HwPfFecUl5gIbDebugReg + ACC_ENGINE_OFFSET * template_idx; + address = VRB1_PfFecUl5gIbDebugReg + ACC_ENGINE_OFFSET * template_idx; status = (acc_reg_read(d, address) >> 4) & 0x7; - address = HWPfQmgrGrpTmplateReg4Indx + address = VRB1_PfQmgrGrpTmplateReg4Indx + ACC_BYTES_IN_WORD * template_idx; if (status == 1) { acc_reg_write(d, address, value); @@ -3606,7 +3604,7 @@ acc200_configure(const char *dev_name, struct rte_acc_conf *conf) for (template_idx = ACC200_SIG_DL_4G; template_idx <= ACC200_SIG_DL_4G_LAST; template_idx++) { - address = HWPfQmgrGrpTmplateReg4Indx + address = VRB1_PfQmgrGrpTmplateReg4Indx + ACC_BYTES_IN_WORD * template_idx; acc_reg_write(d, address, value); } @@ -3619,7 +3617,7 @@ acc200_configure(const char *dev_name, struct rte_acc_conf *conf) for (template_idx = ACC200_SIG_DL_5G; template_idx <= ACC200_SIG_DL_5G_LAST; template_idx++) { - address = HWPfQmgrGrpTmplateReg4Indx + address = VRB1_PfQmgrGrpTmplateReg4Indx + ACC_BYTES_IN_WORD * template_idx; acc_reg_write(d, address, value); } @@ -3632,7 +3630,7 @@ acc200_configure(const char *dev_name, struct rte_acc_conf *conf) for (template_idx = ACC200_SIG_FFT; template_idx <= ACC200_SIG_FFT_LAST; template_idx++) { - address = HWPfQmgrGrpTmplateReg4Indx + address = VRB1_PfQmgrGrpTmplateReg4Indx + ACC_BYTES_IN_WORD * template_idx; acc_reg_write(d, address, value); } @@ -3644,17 +3642,17 @@ acc200_configure(const char *dev_name, struct rte_acc_conf *conf) acc = accFromQgid(qg_idx, conf); value |= qman_func_id[acc] << (qg_idx * 4); } - acc_reg_write(d, HWPfQmgrGrpFunction0, value); + acc_reg_write(d, VRB1_PfQmgrGrpFunction0, value); value = 0; for (qg_idx = 0; qg_idx < ACC_NUM_QGRPS_PER_WORD; qg_idx++) { acc = accFromQgid(qg_idx + ACC_NUM_QGRPS_PER_WORD, conf); value |= qman_func_id[acc] << (qg_idx * 4); } - acc_reg_write(d, HWPfQmgrGrpFunction1, value); + acc_reg_write(d, VRB1_PfQmgrGrpFunction1, value); /* Configuration of the Arbitration QGroup depth to 1. */ for (qg_idx = 0; qg_idx < ACC200_NUM_QGRPS; qg_idx++) { - address = HWPfQmgrArbQDepthGrp + + address = VRB1_PfQmgrArbQDepthGrp + ACC_BYTES_IN_WORD * qg_idx; value = 0; acc_reg_write(d, address, value); @@ -3664,7 +3662,7 @@ acc200_configure(const char *dev_name, struct rte_acc_conf *conf) uint32_t aram_address = 0; for (qg_idx = 0; qg_idx < totalQgs; qg_idx++) { for (vf_idx = 0; vf_idx < conf->num_vf_bundles; vf_idx++) { - address = HWPfQmgrVfBaseAddr + vf_idx + address = VRB1_PfQmgrVfBaseAddr + vf_idx * ACC_BYTES_IN_WORD + qg_idx * ACC_BYTES_IN_WORD * 64; value = aram_address; @@ -3682,36 +3680,36 @@ acc200_configure(const char *dev_name, struct rte_acc_conf *conf) } /* Performance tuning. */ - acc_reg_write(d, HWPfFabricI2Mdma_weight, 0x0FFF); - acc_reg_write(d, HWPfDma4gdlIbThld, 0x1f10); + acc_reg_write(d, VRB1_PfFabricI2Mdma_weight, 0x0FFF); + acc_reg_write(d, VRB1_PfDma4gdlIbThld, 0x1f10); /* ==== HI Configuration ==== */ /* No Info Ring/MSI by default. */ - address = HWPfHiInfoRingIntWrEnRegPf; + address = VRB1_PfHiInfoRingIntWrEnRegPf; value = 0; acc_reg_write(d, address, value); - address = HWPfHiCfgMsiIntWrEnRegPf; + address = VRB1_PfHiCfgMsiIntWrEnRegPf; value = 0xFFFFFFFF; acc_reg_write(d, address, value); /* Prevent Block on Transmit Error. */ - address = HWPfHiBlockTransmitOnErrorEn; + address = VRB1_PfHiBlockTransmitOnErrorEn; value = 0; acc_reg_write(d, address, value); /* Prevents to drop MSI. */ - address = HWPfHiMsiDropEnableReg; + address = VRB1_PfHiMsiDropEnableReg; value = 0; acc_reg_write(d, address, value); /* Set the PF Mode register. */ - address = HWPfHiPfMode; + address = VRB1_PfHiPfMode; value = (conf->pf_mode_en) ? ACC_PF_VAL : 0; acc_reg_write(d, address, value); /* QoS overflow init. */ value = 1; - address = HWPfQosmonAEvalOverflow0; + address = VRB1_PfQosmonAEvalOverflow0; acc_reg_write(d, address, value); - address = HWPfQosmonBEvalOverflow0; + address = VRB1_PfQosmonBEvalOverflow0; acc_reg_write(d, address, value); /* Configure the FFT RAM LUT. */ @@ -3781,10 +3779,10 @@ acc200_configure(const char *dev_name, struct rte_acc_conf *conf) 0x0191F, 0x0178E, 0x015FC, 0x0146A, 0x012D8, 0x01147, 0x00FB5, 0x00E23, 0x00C91, 0x00AFF, 0x0096D, 0x007DB, 0x00648, 0x004B6, 0x00324, 0x00192}; - acc_reg_write(d, HWPfFftRamPageAccess, ACC200_FFT_RAM_EN + 64); + acc_reg_write(d, VRB1_PfFftRamPageAccess, ACC200_FFT_RAM_EN + 64); for (i = 0; i < ACC200_FFT_RAM_SIZE; i++) - acc_reg_write(d, HWPfFftRamOff + i * 4, fft_lut[i]); - acc_reg_write(d, HWPfFftRamPageAccess, ACC200_FFT_RAM_DIS); + acc_reg_write(d, VRB1_PfFftRamOff + i * 4, fft_lut[i]); + acc_reg_write(d, VRB1_PfFftRamPageAccess, ACC200_FFT_RAM_DIS); /* Enabling AQueues through the Queue hierarchy. */ for (vf_idx = 0; vf_idx < ACC200_NUM_VFS; vf_idx++) { @@ -3792,7 +3790,7 @@ acc200_configure(const char *dev_name, struct rte_acc_conf *conf) value = 0; if (vf_idx < conf->num_vf_bundles && qg_idx < totalQgs) value = (1 << aqNum(qg_idx, conf)) - 1; - address = HWPfQmgrAqEnableVf + vf_idx * ACC_BYTES_IN_WORD; + address = VRB1_PfQmgrAqEnableVf + vf_idx * ACC_BYTES_IN_WORD; value += (qg_idx << 16); acc_reg_write(d, address, value); } diff --git a/drivers/baseband/acc/vrb_pmd.h b/drivers/baseband/acc/vrb_pmd.h index 72f92e8414..d4bb16da26 100644 --- a/drivers/baseband/acc/vrb_pmd.h +++ b/drivers/baseband/acc/vrb_pmd.h @@ -128,80 +128,80 @@ struct acc_registry_addr { /* Structure holding registry addresses for PF */ static const struct acc_registry_addr acc200_pf_reg_addr = { - .dma_ring_dl5g_hi = HWPfDmaFec5GdlDescBaseHiRegVf, - .dma_ring_dl5g_lo = HWPfDmaFec5GdlDescBaseLoRegVf, - .dma_ring_ul5g_hi = HWPfDmaFec5GulDescBaseHiRegVf, - .dma_ring_ul5g_lo = HWPfDmaFec5GulDescBaseLoRegVf, - .dma_ring_dl4g_hi = HWPfDmaFec4GdlDescBaseHiRegVf, - .dma_ring_dl4g_lo = HWPfDmaFec4GdlDescBaseLoRegVf, - .dma_ring_ul4g_hi = HWPfDmaFec4GulDescBaseHiRegVf, - .dma_ring_ul4g_lo = HWPfDmaFec4GulDescBaseLoRegVf, - .dma_ring_fft_hi = HWPfDmaFftDescBaseHiRegVf, - .dma_ring_fft_lo = HWPfDmaFftDescBaseLoRegVf, - .ring_size = HWPfQmgrRingSizeVf, - .info_ring_hi = HWPfHiInfoRingBaseHiRegPf, - .info_ring_lo = HWPfHiInfoRingBaseLoRegPf, - .info_ring_en = HWPfHiInfoRingIntWrEnRegPf, - .info_ring_ptr = HWPfHiInfoRingPointerRegPf, - .tail_ptrs_dl5g_hi = HWPfDmaFec5GdlRespPtrHiRegVf, - .tail_ptrs_dl5g_lo = HWPfDmaFec5GdlRespPtrLoRegVf, - .tail_ptrs_ul5g_hi = HWPfDmaFec5GulRespPtrHiRegVf, - .tail_ptrs_ul5g_lo = HWPfDmaFec5GulRespPtrLoRegVf, - .tail_ptrs_dl4g_hi = HWPfDmaFec4GdlRespPtrHiRegVf, - .tail_ptrs_dl4g_lo = HWPfDmaFec4GdlRespPtrLoRegVf, - .tail_ptrs_ul4g_hi = HWPfDmaFec4GulRespPtrHiRegVf, - .tail_ptrs_ul4g_lo = HWPfDmaFec4GulRespPtrLoRegVf, - .tail_ptrs_fft_hi = HWPfDmaFftRespPtrHiRegVf, - .tail_ptrs_fft_lo = HWPfDmaFftRespPtrLoRegVf, - .depth_log0_offset = HWPfQmgrGrpDepthLog20Vf, - .depth_log1_offset = HWPfQmgrGrpDepthLog21Vf, - .qman_group_func = HWPfQmgrGrpFunction0, - .hi_mode = HWPfHiMsixVectorMapperPf, - .pf_mode = HWPfHiPfMode, - .pmon_ctrl_a = HWPfPermonACntrlRegVf, - .pmon_ctrl_b = HWPfPermonBCntrlRegVf, - .pmon_ctrl_c = HWPfPermonCCntrlRegVf, + .dma_ring_dl5g_hi = VRB1_PfDmaFec5GdlDescBaseHiRegVf, + .dma_ring_dl5g_lo = VRB1_PfDmaFec5GdlDescBaseLoRegVf, + .dma_ring_ul5g_hi = VRB1_PfDmaFec5GulDescBaseHiRegVf, + .dma_ring_ul5g_lo = VRB1_PfDmaFec5GulDescBaseLoRegVf, + .dma_ring_dl4g_hi = VRB1_PfDmaFec4GdlDescBaseHiRegVf, + .dma_ring_dl4g_lo = VRB1_PfDmaFec4GdlDescBaseLoRegVf, + .dma_ring_ul4g_hi = VRB1_PfDmaFec4GulDescBaseHiRegVf, + .dma_ring_ul4g_lo = VRB1_PfDmaFec4GulDescBaseLoRegVf, + .dma_ring_fft_hi = VRB1_PfDmaFftDescBaseHiRegVf, + .dma_ring_fft_lo = VRB1_PfDmaFftDescBaseLoRegVf, + .ring_size = VRB1_PfQmgrRingSizeVf, + .info_ring_hi = VRB1_PfHiInfoRingBaseHiRegPf, + .info_ring_lo = VRB1_PfHiInfoRingBaseLoRegPf, + .info_ring_en = VRB1_PfHiInfoRingIntWrEnRegPf, + .info_ring_ptr = VRB1_PfHiInfoRingPointerRegPf, + .tail_ptrs_dl5g_hi = VRB1_PfDmaFec5GdlRespPtrHiRegVf, + .tail_ptrs_dl5g_lo = VRB1_PfDmaFec5GdlRespPtrLoRegVf, + .tail_ptrs_ul5g_hi = VRB1_PfDmaFec5GulRespPtrHiRegVf, + .tail_ptrs_ul5g_lo = VRB1_PfDmaFec5GulRespPtrLoRegVf, + .tail_ptrs_dl4g_hi = VRB1_PfDmaFec4GdlRespPtrHiRegVf, + .tail_ptrs_dl4g_lo = VRB1_PfDmaFec4GdlRespPtrLoRegVf, + .tail_ptrs_ul4g_hi = VRB1_PfDmaFec4GulRespPtrHiRegVf, + .tail_ptrs_ul4g_lo = VRB1_PfDmaFec4GulRespPtrLoRegVf, + .tail_ptrs_fft_hi = VRB1_PfDmaFftRespPtrHiRegVf, + .tail_ptrs_fft_lo = VRB1_PfDmaFftRespPtrLoRegVf, + .depth_log0_offset = VRB1_PfQmgrGrpDepthLog20Vf, + .depth_log1_offset = VRB1_PfQmgrGrpDepthLog21Vf, + .qman_group_func = VRB1_PfQmgrGrpFunction0, + .hi_mode = VRB1_PfHiMsixVectorMapperPf, + .pf_mode = VRB1_PfHiPfMode, + .pmon_ctrl_a = VRB1_PfPermonACntrlRegVf, + .pmon_ctrl_b = VRB1_PfPermonBCntrlRegVf, + .pmon_ctrl_c = VRB1_PfPermonCCntrlRegVf, .vf2pf_doorbell = 0, .pf2vf_doorbell = 0, }; /* Structure holding registry addresses for VF */ static const struct acc_registry_addr acc200_vf_reg_addr = { - .dma_ring_dl5g_hi = HWVfDmaFec5GdlDescBaseHiRegVf, - .dma_ring_dl5g_lo = HWVfDmaFec5GdlDescBaseLoRegVf, - .dma_ring_ul5g_hi = HWVfDmaFec5GulDescBaseHiRegVf, - .dma_ring_ul5g_lo = HWVfDmaFec5GulDescBaseLoRegVf, - .dma_ring_dl4g_hi = HWVfDmaFec4GdlDescBaseHiRegVf, - .dma_ring_dl4g_lo = HWVfDmaFec4GdlDescBaseLoRegVf, - .dma_ring_ul4g_hi = HWVfDmaFec4GulDescBaseHiRegVf, - .dma_ring_ul4g_lo = HWVfDmaFec4GulDescBaseLoRegVf, - .dma_ring_fft_hi = HWVfDmaFftDescBaseHiRegVf, - .dma_ring_fft_lo = HWVfDmaFftDescBaseLoRegVf, - .ring_size = HWVfQmgrRingSizeVf, - .info_ring_hi = HWVfHiInfoRingBaseHiVf, - .info_ring_lo = HWVfHiInfoRingBaseLoVf, - .info_ring_en = HWVfHiInfoRingIntWrEnVf, - .info_ring_ptr = HWVfHiInfoRingPointerVf, - .tail_ptrs_dl5g_hi = HWVfDmaFec5GdlRespPtrHiRegVf, - .tail_ptrs_dl5g_lo = HWVfDmaFec5GdlRespPtrLoRegVf, - .tail_ptrs_ul5g_hi = HWVfDmaFec5GulRespPtrHiRegVf, - .tail_ptrs_ul5g_lo = HWVfDmaFec5GulRespPtrLoRegVf, - .tail_ptrs_dl4g_hi = HWVfDmaFec4GdlRespPtrHiRegVf, - .tail_ptrs_dl4g_lo = HWVfDmaFec4GdlRespPtrLoRegVf, - .tail_ptrs_ul4g_hi = HWVfDmaFec4GulRespPtrHiRegVf, - .tail_ptrs_ul4g_lo = HWVfDmaFec4GulRespPtrLoRegVf, - .tail_ptrs_fft_hi = HWVfDmaFftRespPtrHiRegVf, - .tail_ptrs_fft_lo = HWVfDmaFftRespPtrLoRegVf, - .depth_log0_offset = HWVfQmgrGrpDepthLog20Vf, - .depth_log1_offset = HWVfQmgrGrpDepthLog21Vf, - .qman_group_func = HWVfQmgrGrpFunction0Vf, - .hi_mode = HWVfHiMsixVectorMapperVf, + .dma_ring_dl5g_hi = VRB1_VfDmaFec5GdlDescBaseHiRegVf, + .dma_ring_dl5g_lo = VRB1_VfDmaFec5GdlDescBaseLoRegVf, + .dma_ring_ul5g_hi = VRB1_VfDmaFec5GulDescBaseHiRegVf, + .dma_ring_ul5g_lo = VRB1_VfDmaFec5GulDescBaseLoRegVf, + .dma_ring_dl4g_hi = VRB1_VfDmaFec4GdlDescBaseHiRegVf, + .dma_ring_dl4g_lo = VRB1_VfDmaFec4GdlDescBaseLoRegVf, + .dma_ring_ul4g_hi = VRB1_VfDmaFec4GulDescBaseHiRegVf, + .dma_ring_ul4g_lo = VRB1_VfDmaFec4GulDescBaseLoRegVf, + .dma_ring_fft_hi = VRB1_VfDmaFftDescBaseHiRegVf, + .dma_ring_fft_lo = VRB1_VfDmaFftDescBaseLoRegVf, + .ring_size = VRB1_VfQmgrRingSizeVf, + .info_ring_hi = VRB1_VfHiInfoRingBaseHiVf, + .info_ring_lo = VRB1_VfHiInfoRingBaseLoVf, + .info_ring_en = VRB1_VfHiInfoRingIntWrEnVf, + .info_ring_ptr = VRB1_VfHiInfoRingPointerVf, + .tail_ptrs_dl5g_hi = VRB1_VfDmaFec5GdlRespPtrHiRegVf, + .tail_ptrs_dl5g_lo = VRB1_VfDmaFec5GdlRespPtrLoRegVf, + .tail_ptrs_ul5g_hi = VRB1_VfDmaFec5GulRespPtrHiRegVf, + .tail_ptrs_ul5g_lo = VRB1_VfDmaFec5GulRespPtrLoRegVf, + .tail_ptrs_dl4g_hi = VRB1_VfDmaFec4GdlRespPtrHiRegVf, + .tail_ptrs_dl4g_lo = VRB1_VfDmaFec4GdlRespPtrLoRegVf, + .tail_ptrs_ul4g_hi = VRB1_VfDmaFec4GulRespPtrHiRegVf, + .tail_ptrs_ul4g_lo = VRB1_VfDmaFec4GulRespPtrLoRegVf, + .tail_ptrs_fft_hi = VRB1_VfDmaFftRespPtrHiRegVf, + .tail_ptrs_fft_lo = VRB1_VfDmaFftRespPtrLoRegVf, + .depth_log0_offset = VRB1_VfQmgrGrpDepthLog20Vf, + .depth_log1_offset = VRB1_VfQmgrGrpDepthLog21Vf, + .qman_group_func = VRB1_VfQmgrGrpFunction0Vf, + .hi_mode = VRB1_VfHiMsixVectorMapperVf, .pf_mode = 0, - .pmon_ctrl_a = HWVfPmACntrlRegVf, - .pmon_ctrl_b = HWVfPmBCntrlRegVf, - .pmon_ctrl_c = HWVfPmCCntrlRegVf, - .vf2pf_doorbell = HWVfHiVfToPfDbellVf, - .pf2vf_doorbell = HWVfHiPfToVfDbellVf, + .pmon_ctrl_a = VRB1_VfPmACntrlRegVf, + .pmon_ctrl_b = VRB1_VfPmBCntrlRegVf, + .pmon_ctrl_c = VRB1_VfPmCCntrlRegVf, + .vf2pf_doorbell = VRB1_VfHiVfToPfDbellVf, + .pf2vf_doorbell = VRB1_VfHiPfToVfDbellVf, }; #endif /* _VRB_PMD_H_ */