From patchwork Tue Jan 17 13:26:18 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simei Su X-Patchwork-Id: 122186 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 63427423FD; Tue, 17 Jan 2023 14:27:12 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 5888442D32; Tue, 17 Jan 2023 14:27:02 +0100 (CET) Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by mails.dpdk.org (Postfix) with ESMTP id 02FA2410DD for ; Tue, 17 Jan 2023 14:27:00 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1673962021; x=1705498021; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=93BSCUp+mEHJb0gbYju+6anF8YSA3qzSnoFH11jcEoc=; b=U+QxT02hANFKmaehDjt/OzFneMTW7/rpRA+YfZC4L4A8iTW6J0YhvfEj lI/03+Qol7q7iQqRhxTkaZiZ+QDiVs7bYYwayFUckyectm96N6lWrplCT p22tfn1ZMnA4JvS62hvSMMP/4eE1fTP2xMb43uepwH5a8WkYEVQinRdCP kX/Jw8VZ7ecFNlkTMqSPwABpOz4YPdPmJXdulT3dtaMaJ/OLYU+hjnHjQ TrxXsjTeCOV5xmcTYl/owCweZgw8EsKEXwoXoaWs3Sw6mpaCiGXKnakDY WlRYfGusu1TQf9/VAJE3MKOT5v4Gyp3tvKFHsYuMgJMgheSQZE4VQh0QY g==; X-IronPort-AV: E=McAfee;i="6500,9779,10592"; a="308255774" X-IronPort-AV: E=Sophos;i="5.97,224,1669104000"; d="scan'208";a="308255774" Received: from orsmga002.jf.intel.com ([10.7.209.21]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Jan 2023 05:27:00 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10592"; a="659392196" X-IronPort-AV: E=Sophos;i="5.97,224,1669104000"; d="scan'208";a="659392196" Received: from unknown (HELO npg-dpdk-simeisu-cvl-119d218.sh.intel.com) ([10.67.119.208]) by orsmga002.jf.intel.com with ESMTP; 17 Jan 2023 05:26:58 -0800 From: Simei Su To: qi.z.zhang@intel.com, junfeng.guo@intel.com Cc: dev@dpdk.org, wenjun1.wu@intel.com, Simei Su Subject: [PATCH v2 2/3] net/igc/base: support PTP timesync Date: Tue, 17 Jan 2023 21:26:18 +0800 Message-Id: <20230117132619.83712-3-simei.su@intel.com> X-Mailer: git-send-email 2.9.5 In-Reply-To: <20230117132619.83712-1-simei.su@intel.com> References: <20221220034103.441524-1-simei.su@intel.com> <20230117132619.83712-1-simei.su@intel.com> X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Add definitions for timesync enabling. Signed-off-by: Simei Su --- drivers/net/igc/base/igc_defines.h | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/drivers/net/igc/base/igc_defines.h b/drivers/net/igc/base/igc_defines.h index 61964bc..dd7330a 100644 --- a/drivers/net/igc/base/igc_defines.h +++ b/drivers/net/igc/base/igc_defines.h @@ -795,6 +795,17 @@ #define TSYNC_INTERRUPTS TSINTR_TXTS +/* Split Replication Receive Control */ +#define IGC_SRRCTL_TIMESTAMP 0x40000000 +#define IGC_SRRCTL_TIMER1SEL(timer) (((timer) & 0x3) << 14) +#define IGC_SRRCTL_TIMER0SEL(timer) (((timer) & 0x3) << 17) + +/* Sample RX tstamp in PHY sop */ +#define IGC_TSYNCRXCTL_RXSYNSIG 0x00000400 + +/* Sample TX tstamp in PHY sop */ +#define IGC_TSYNCTXCTL_TXSYNSIG 0x00000020 + /* TSAUXC Configuration Bits */ #define TSAUXC_EN_TT0 (1 << 0) /* Enable target time 0. */ #define TSAUXC_EN_TT1 (1 << 1) /* Enable target time 1. */