[3/9] common/cnxk: configure fc hist bits
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Commit Message
From: Satha Rao <skoteshwar@marvell.com>
New parameter added inside SQ structure to control the fc_hyst_bits.
Instead of count on all updates each SQ can tune his own hysteresis
level.
Signed-off-by: Satha Rao <skoteshwar@marvell.com>
---
drivers/common/cnxk/roc_nix.h | 1 +
drivers/common/cnxk/roc_nix_queue.c | 5 ++---
2 files changed, 3 insertions(+), 3 deletions(-)
@@ -354,6 +354,7 @@ struct roc_nix_sq {
uint16_t cq_drop_thresh;
bool sso_ena;
bool cq_ena;
+ uint8_t fc_hyst_bits;
/* End of Input parameters */
uint16_t sqes_per_sqb_log2;
struct roc_nix *roc_nix;
@@ -1025,9 +1025,8 @@ sqb_pool_populate(struct roc_nix *roc_nix, struct roc_nix_sq *sq)
else
aura.fc_stype = 0x3; /* STSTP */
aura.fc_addr = (uint64_t)sq->fc;
- aura.fc_hyst_bits = 1; /* Store count on all updates */
- rc = roc_npa_pool_create(&sq->aura_handle, blk_sz, nb_sqb_bufs, &aura,
- &pool, 0);
+ aura.fc_hyst_bits = sq->fc_hyst_bits & 0xF;
+ rc = roc_npa_pool_create(&sq->aura_handle, blk_sz, nb_sqb_bufs, &aura, &pool, 0);
if (rc)
goto fail;