From patchwork Tue Dec 20 03:41:02 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simei Su X-Patchwork-Id: 121049 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id B3CF5A00C5; Tue, 20 Dec 2022 04:41:38 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 4DA1640A7F; Tue, 20 Dec 2022 04:41:32 +0100 (CET) Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by mails.dpdk.org (Postfix) with ESMTP id CFE3540698 for ; Tue, 20 Dec 2022 04:41:30 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1671507691; x=1703043691; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=93BSCUp+mEHJb0gbYju+6anF8YSA3qzSnoFH11jcEoc=; b=m/OdPpq9ua7TaZKuUmseFp++4tiiRsa/jRMNatJDU0RolY+E7lyj/hsb E9z7I6RdAP99qoIRc5Obmj9YpnHTnmwEHwXe9LCph/K+ku64QETN3CIYj xfWftv13QJGaFMyn5AOxijq+a6zQ1E5lwcJEKRGwcmQ3YQqdfud8xKCAX P4lbR5/wIpHOdTVnNcVxg2zfba1RIa8b8bqcMPYCM9deE1xukRptRW1UF O/dvsgSD+sqixzc/UjGkeAjQFGAGDIGCRBDbJhwxRWKREUL4S1GbKBdOy sEELQuKZEkMr5ipwY5NGYu92RUj9qifyj1uCQOyWhGJdM64iB3WbDyI2+ A==; X-IronPort-AV: E=McAfee;i="6500,9779,10566"; a="307201131" X-IronPort-AV: E=Sophos;i="5.96,258,1665471600"; d="scan'208";a="307201131" Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Dec 2022 19:41:30 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10566"; a="683267309" X-IronPort-AV: E=Sophos;i="5.96,258,1665471600"; d="scan'208";a="683267309" Received: from unknown (HELO npg-dpdk-simeisu-cvl-119d218.sh.intel.com) ([10.67.119.208]) by orsmga001.jf.intel.com with ESMTP; 19 Dec 2022 19:41:27 -0800 From: Simei Su To: qi.z.zhang@intel.com, junfeng.guo@intel.com Cc: dev@dpdk.org, wenjun1.wu@intel.com, Simei Su Subject: [PATCH 2/3] net/igc/base: support PTP timesync Date: Tue, 20 Dec 2022 11:41:02 +0800 Message-Id: <20221220034103.441524-3-simei.su@intel.com> X-Mailer: git-send-email 2.9.5 In-Reply-To: <20221220034103.441524-1-simei.su@intel.com> References: <20221220034103.441524-1-simei.su@intel.com> X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Add definitions for timesync enabling. Signed-off-by: Simei Su --- drivers/net/igc/base/igc_defines.h | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/drivers/net/igc/base/igc_defines.h b/drivers/net/igc/base/igc_defines.h index 61964bc..dd7330a 100644 --- a/drivers/net/igc/base/igc_defines.h +++ b/drivers/net/igc/base/igc_defines.h @@ -795,6 +795,17 @@ #define TSYNC_INTERRUPTS TSINTR_TXTS +/* Split Replication Receive Control */ +#define IGC_SRRCTL_TIMESTAMP 0x40000000 +#define IGC_SRRCTL_TIMER1SEL(timer) (((timer) & 0x3) << 14) +#define IGC_SRRCTL_TIMER0SEL(timer) (((timer) & 0x3) << 17) + +/* Sample RX tstamp in PHY sop */ +#define IGC_TSYNCRXCTL_RXSYNSIG 0x00000400 + +/* Sample TX tstamp in PHY sop */ +#define IGC_TSYNCTXCTL_TXSYNSIG 0x00000020 + /* TSAUXC Configuration Bits */ #define TSAUXC_EN_TT0 (1 << 0) /* Enable target time 0. */ #define TSAUXC_EN_TT1 (1 << 1) /* Enable target time 1. */